View R5F21258SDFP_4329137.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

REJ09B0244-0300
16
R8C/24 Group, R8C/25 Group
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES
All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).
Rev.3.00 Revision Date: Feb 29, 2008
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the R8C/24 Group, R8C/25 Group. Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Document Type Datasheet Description Document Title Document No. Hardware overview and electrical characteristics R8C/24 Group, REJ03B0117 R8C/25 Group Datasheet R8C/24 Group, This hardware Hardware manual Hardware specifications (pin assignments, R8C/25 Group manual memory maps, peripheral function Hardware Manual specifications, electrical characteristics, timing charts) and operation description Note: Refer to the application notes for details on using peripheral functions. Software manual Description of CPU instruction set R8C/Tiny Series REJ09B0001 Software Manual Available from Renesas Application note Information on using peripheral functions and Technology Web site. application examples Sample programs Information on writing programs in assembly language and C Renesas Product specifications, updates on documents, technical update etc.
2.
Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word "register," "bit," or "pin" to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin Notation of Numbers The indication "b" is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication "h" is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234
(2)
3.
Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
*1
Symbol XXX Address XXX After Reset 00h
0
Bit Symbol
XXX0
Bit Name
XXX bits
b1 b0
Function
1 0: XXX 0 1: XXX 1 0: Do not set. 1 1: XXX
RW RW
*2
XXX1
RW
(b2)
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
*3
RW
(b3)
Reserved bits
Set to 0.
*4
XXX4
XXX bits
Function varies according to the operating mode.
RW
XXX5
WO
XXX6 0: XXX 1: XXX
RW
XXX7
XXX bit
RO
*1 Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Nothing is assigned. *2 RW: Read and write. RO: Read only. WO: Write only. -: Nothing is assigned. *3 * Reserved bit Reserved bit. Set to specified value. *4 * Nothing is assigned Nothing is assigned to the bit. As the bit may be used for future functions, if necessary, set to 0. * Do not set to a value Operation is not guaranteed when a value is set. * Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes.
4.
List of Abbreviations and Acronyms
Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment bus Input/Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connection Phase Locked Loop Pulse Width Modulation Special Function Registers Subscriber Identity Module Universal Asynchronous Receiver/Transmitter Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners.
Table of Contents
SFR Page Reference ........................................................................................................................... B - 1 1. 1.1 1.2 1.3 1.4 1.5 1.6 2. Overview ......................................................................................................................................... 1 Applications ............................................................................................................................................... 1 Performance Overview .............................................................................................................................. 2 Block Diagram .......................................................................................................................................... 4 Product Information .................................................................................................................................. 5 Pin Assignments ........................................................................................................................................ 9 Pin Functions ........................................................................................................................................... 11 Central Processing Unit (CPU) ..................................................................................................... 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.8.6 2.8.7 2.8.8 2.8.9 2.8.10 3. 3.1 3.2 4. 5. Data Registers (R0, R1, R2, and R3) ...................................................................................................... Address Registers (A0 and A1) ............................................................................................................... Frame Base Register (FB) ....................................................................................................................... Interrupt Table Register (INTB) .............................................................................................................. Program Counter (PC) ............................................................................................................................. User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................................. Static Base Register (SB) ........................................................................................................................ Flag Register (FLG) ................................................................................................................................ Carry Flag (C) ..................................................................................................................................... Debug Flag (D) ................................................................................................................................... Zero Flag (Z) ....................................................................................................................................... Sign Flag (S) ....................................................................................................................................... Register Bank Select Flag (B) ............................................................................................................ Overflow Flag (O) .............................................................................................................................. Interrupt Enable Flag (I) ..................................................................................................................... Stack Pointer Select Flag (U) .............................................................................................................. Processor Interrupt Priority Level (IPL) ............................................................................................. Reserved Bit ........................................................................................................................................ 14 14 14 14 14 14 14 14 14 14 14 14 14 14 15 15 15 15
Memory ......................................................................................................................................... 16 R8C/24 Group ......................................................................................................................................... 16 R8C/25 Group ......................................................................................................................................... 17 Special Function Registers (SFRs) ............................................................................................... 18 Resets ........................................................................................................................................... 25 5.1 5.1.1 5.1.2 5.2 5.3 5.4 5.5 5.6 5.7 Hardware Reset ....................................................................................................................................... When Power Supply is Stable ............................................................................................................. Power On ............................................................................................................................................ Power-On Reset Function ....................................................................................................................... Voltage Monitor 0 Reset ......................................................................................................................... Voltage Monitor 1 Reset ......................................................................................................................... Voltage Monitor 2 Reset ......................................................................................................................... Watchdog Timer Reset ............................................................................................................................ Software Reset ......................................................................................................................................... 28 28 28 30 31 31 31 32 32
6. 6.1
Voltage Detection Circuit .............................................................................................................. 33 VCC Input Voltage .................................................................................................................................. 40 A-1
6.1.1 Monitoring Vdet0 ............................................................................................................................... 6.1.2 Monitoring Vdet1 ............................................................................................................................... 6.1.3 Monitoring Vdet2 ............................................................................................................................... 6.2 Voltage Monitor 0 Reset ......................................................................................................................... 6.3 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset ..................................................................... 6.4 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset ..................................................................... 7. 7.1 7.2 7.3 7.4 7.5 8. 8.1 9. 10.
40 40 40 41 42 44
Programmable I/O Ports ............................................................................................................... 46 Functions of Programmable I/O Ports ..................................................................................................... Effect on Peripheral Functions ................................................................................................................ Pins Other than Programmable I/O Ports ................................................................................................ Port settings ............................................................................................................................................. Unassigned Pin Handling ........................................................................................................................ 46 47 47 59 70
Processor Mode ............................................................................................................................ 71 Processor Modes ...................................................................................................................................... 71 Bus ................................................................................................................................................ 72 Clock Generation Circuit ............................................................................................................... 73 XIN Clock ............................................................................................................................................... On-Chip Oscillator Clocks ...................................................................................................................... Low-Speed On-Chip Oscillator Clock ................................................................................................ High-Speed On-Chip Oscillator Clock ............................................................................................... XCIN Clock ............................................................................................................................................. CPU Clock and Peripheral Function Clock ............................................................................................. System Clock ...................................................................................................................................... CPU Clock .......................................................................................................................................... Peripheral Function Clock (f1, f2, f4, f8, and f32) ............................................................................. fOCO ................................................................................................................................................... fOCO40M ........................................................................................................................................... fOCO-F ............................................................................................................................................... fOCO-S ............................................................................................................................................... fOCO128 ............................................................................................................................................. fC4 and fC32 ....................................................................................................................................... Power Control .......................................................................................................................................... Standard Operating Mode ................................................................................................................... Wait Mode .......................................................................................................................................... Stop Mode ........................................................................................................................................... Oscillation Stop Detection Function ....................................................................................................... How to Use Oscillation Stop Detection Function ............................................................................... Notes on Clock Generation Circuit ......................................................................................................... Stop Mode ........................................................................................................................................... Wait Mode .......................................................................................................................................... Oscillation Stop Detection Function ................................................................................................... Oscillation Circuit Constants .............................................................................................................. 82 83 83 83 84 85 85 85 85 85 85 85 85 85 86 87 87 89 93 96 96 99 99 99 99 99
10.1 10.2 10.2.1 10.2.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.4.9 10.5 10.5.1 10.5.2 10.5.3 10.6 10.6.1 10.7 10.7.1 10.7.2 10.7.3 10.7.4
A-2
11. 12.
Protection .................................................................................................................................... 100 Interrupts ..................................................................................................................................... 101 Interrupt Overview ................................................................................................................................ 101 Types of Interrupts ............................................................................................................................ 101 Software Interrupts ........................................................................................................................... 102 Special Interrupts .............................................................................................................................. 103 Peripheral Function Interrupt ............................................................................................................ 103 Interrupts and Interrupt Vectors ........................................................................................................ 104 Interrupt Control ............................................................................................................................... 106 INT Interrupt ......................................................................................................................................... 115 INTi Interrupt (i = 0 to 3) .................................................................................................................. 115 INTi Input Filter (i = 0 to 3) .............................................................................................................. 117 Key Input Interrupt ................................................................................................................................ 118 Address Match Interrupt ........................................................................................................................ 120 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request Sources) ............................................................ 122 Notes on Interrupts ................................................................................................................................ 124 Reading Address 00000h .................................................................................................................. 124 SP Setting .......................................................................................................................................... 124 External Interrupt and Key Input Interrupt ....................................................................................... 124 Changing Interrupt Sources .............................................................................................................. 125 Changing Interrupt Control Register Contents ................................................................................. 126
12.1 12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 12.1.6 12.2 12.2.1 12.2.2 12.3 12.4 12.5 12.6 12.6.1 12.6.2 12.6.3 12.6.4 12.6.5 13. 13.1 13.2 14.
Watchdog Timer .......................................................................................................................... 127 Count Source Protection Mode Disabled .............................................................................................. 130 Count Source Protection Mode Enabled ............................................................................................... 131 Timers ......................................................................................................................................... 132
14.1 Timer RA ............................................................................................................................................... 134 14.1.1 Timer Mode ...................................................................................................................................... 137 14.1.2 Pulse Output Mode ........................................................................................................................... 139 14.1.3 Event Counter Mode ......................................................................................................................... 141 14.1.4 Pulse Width Measurement Mode ...................................................................................................... 143 14.1.5 Pulse Period Measurement Mode ..................................................................................................... 146 14.1.6 Notes on Timer RA ........................................................................................................................... 149 14.2 Timer RB ............................................................................................................................................... 150 14.2.1 Timer Mode ...................................................................................................................................... 154 14.2.2 Programmable Waveform Generation Mode .................................................................................... 157 14.2.3 Programmable One-shot Generation Mode ...................................................................................... 159 14.2.4 Programmable Wait One-Shot Generation Mode ............................................................................. 163 14.2.5 Notes on Timer RB ........................................................................................................................... 167 14.3 Timer RD ............................................................................................................................................... 171 14.3.1 Count Sources ................................................................................................................................... 176 14.3.2 Buffer Operation ............................................................................................................................... 177 14.3.3 Synchronous Operation ..................................................................................................................... 179 14.3.4 Pulse Output Forced Cutoff .............................................................................................................. 180 14.3.5 Input Capture Function ..................................................................................................................... 182 14.3.6 Output Compare Function ................................................................................................................ 196 A-3
14.3.7 PWM Mode ....................................................................................................................................... 14.3.8 Reset Synchronous PWM Mode ....................................................................................................... 14.3.9 Complementary PWM Mode ............................................................................................................ 14.3.10 PWM3 Mode ..................................................................................................................................... 14.3.11 Timer RD Interrupt ........................................................................................................................... 14.3.12 Notes on Timer RD ........................................................................................................................... 14.4 Timer RE ............................................................................................................................................... 14.4.1 Real-Time Clock Mode .................................................................................................................... 14.4.2 Output Compare Mode ..................................................................................................................... 14.4.3 Notes on Timer RE ........................................................................................................................... 15.
213 226 236 250 262 264 270 271 279 285
Serial Interface ............................................................................................................................ 288 294 297 297 298 299 303 304
15.1 Clock Synchronous Serial I/O Mode ..................................................................................................... 15.1.1 Polarity Select Function .................................................................................................................... 15.1.2 LSB First/MSB First Select Function ............................................................................................... 15.1.3 Continuous Receive Mode ................................................................................................................ 15.2 Clock Asynchronous Serial I/O (UART) Mode .................................................................................... 15.2.1 Bit Rate ............................................................................................................................................. 15.3 Notes on Serial Interface ....................................................................................................................... 16.
Clock Synchronous Serial Interface ............................................................................................ 305 Mode Selection ...................................................................................................................................... Clock Synchronous Serial I/O with Chip Select (SSU) ........................................................................ Transfer Clock .................................................................................................................................. SS Shift Register (SSTRSR) ............................................................................................................. Interrupt Requests ............................................................................................................................. Communication Modes and Pin Functions ....................................................................................... Clock Synchronous Communication Mode ...................................................................................... Operation in 4-Wire Bus Communication Mode .............................................................................. SCS Pin Control and Arbitration ...................................................................................................... Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... I2C bus Interface .................................................................................................................................... Transfer Clock .................................................................................................................................. Interrupt Requests ............................................................................................................................. I2C bus Interface Mode ..................................................................................................................... Clock Synchronous Serial Mode ...................................................................................................... Noise Canceller ................................................................................................................................. Bit Synchronization Circuit .............................................................................................................. Examples of Register Setting ............................................................................................................ Notes on I2C bus Interface ................................................................................................................ 305 306 315 317 318 319 320 327 333 334 335 345 346 347 358 361 362 363 367
16.1 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.2.5 16.2.6 16.2.7 16.2.8 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.3.7 16.3.8 17.
Hardware LIN .............................................................................................................................. 368 Features ................................................................................................................................................. Input/Output Pins .................................................................................................................................. Register Configuration .......................................................................................................................... Functional Description .......................................................................................................................... Master Mode ..................................................................................................................................... Slave Mode ....................................................................................................................................... Bus Collision Detection Function ..................................................................................................... A-4 368 369 370 372 372 375 379
17.1 17.2 17.3 17.4 17.4.1 17.4.2 17.4.3
17.4.4 Hardware LIN End Processing ......................................................................................................... 380 17.5 Interrupt Requests .................................................................................................................................. 381 17.6 Notes on Hardware LIN ........................................................................................................................ 382 18. 18.1 18.2 18.3 18.4 18.5 18.6 18.7 19. A/D Converter ............................................................................................................................. 383 One-Shot Mode ..................................................................................................................................... Repeat Mode .......................................................................................................................................... Sample and Hold ................................................................................................................................... A/D Conversion Cycles ......................................................................................................................... Internal Equivalent Circuit of Analog Input .......................................................................................... Output Impedance of Sensor under A/D Conversion ............................................................................ Notes on A/D Converter ........................................................................................................................ 387 390 393 393 394 395 396
Flash Memory ............................................................................................................................. 397 Overview ............................................................................................................................................... Memory Map ......................................................................................................................................... Functions to Prevent Rewriting of Flash Memory ................................................................................ ID Code Check Function .................................................................................................................. ROM Code Protect Function ............................................................................................................ CPU Rewrite Mode ............................................................................................................................... EW0 Mode ........................................................................................................................................ EW1 Mode ........................................................................................................................................ Software Commands ......................................................................................................................... Status Registers ................................................................................................................................. Full Status Check .............................................................................................................................. Standard Serial I/O Mode ...................................................................................................................... ID Code Check Function .................................................................................................................. Parallel I/O Mode .................................................................................................................................. ROM Code Protect Function ............................................................................................................ Notes on Flash Memory ........................................................................................................................ CPU Rewrite Mode ........................................................................................................................... 397 398 400 400 401 402 403 403 412 417 418 420 420 424 424 425 425
19.1 19.2 19.3 19.3.1 19.3.2 19.4 19.4.1 19.4.2 19.4.3 19.4.4 19.4.5 19.5 19.5.1 19.6 19.6.1 19.7 19.7.1 20. 21.
Electrical Characteristics ............................................................................................................ 428 Usage Notes ............................................................................................................................... 454
21.1 Notes on Clock Generation Circuit ....................................................................................................... 454 21.1.1 Stop Mode ......................................................................................................................................... 454 21.1.2 Wait Mode ........................................................................................................................................ 454 21.1.3 Oscillation Stop Detection Function ................................................................................................. 454 21.1.4 Oscillation Circuit Constants ............................................................................................................ 454 21.2 Notes on Interrupts ................................................................................................................................ 455 21.2.1 Reading Address 00000h .................................................................................................................. 455 21.2.2 SP Setting .......................................................................................................................................... 455 21.2.3 External Interrupt and Key Input Interrupt ....................................................................................... 455 21.2.4 Changing Interrupt Sources .............................................................................................................. 456 21.2.5 Changing Interrupt Control Register Contents ................................................................................. 457 21.3 Notes on Timers .................................................................................................................................... 458 21.3.1 Notes on Timer RA ........................................................................................................................... 458 21.3.2 Notes on Timer RB ........................................................................................................................... 459 A-5
21.3.3 21.3.4 21.4 21.5 21.5.1 21.5.2 21.6 21.7 21.8 21.8.1 21.9 21.9.1
Notes on Timer RD ........................................................................................................................... 463 Notes on Timer RE ........................................................................................................................... 469 Notes on Serial Interface ....................................................................................................................... 472 Notes on Clock Synchronous Serial Interface ....................................................................................... 473 Notes on Clock Synchronous Serial I/O with Chip Select ............................................................... 473 Notes on I2C bus Interface ................................................................................................................ 473 Notes on Hardware LIN ........................................................................................................................ 474 Notes on A/D Converter ........................................................................................................................ 475 Notes on Flash Memory ........................................................................................................................ 476 CPU Rewrite Mode ........................................................................................................................... 476 Notes on Noise ...................................................................................................................................... 479 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up ............................................................................................................................................ 479 21.9.2 Countermeasures against Noise Error of Port Control Registers ..................................................... 479 Notes on On-Chip Debugger ...................................................................................................... 480
22.
Appendix 1. Package Dimensions ........................................................................................................ 481 Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 482 Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 483 Index ..................................................................................................................................................... 484
A-6
SFR Page Reference
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch High-Speed On-Chip Oscillator Control Register 6 High-Speed On-Chip Oscillator Control Register 7 FRA6 FRA7 79 79 Clock Prescaler Reset Flag High-Speed On-Chip Oscillator Control Register 4 CPSRF FRA4 80 79 High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 FRA0 FRA1 FRA2 78 78 79 Count Source Protection Mode Register CSPR 129 Address Match Interrupt Enable Register Address Match Interrupt Register 1 AIER RMAD1 121 121 Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 OCD WDTR WDTS WDC RMAD0 77 129 129 128 121 Protect Register PRCR 100 Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 71 71 75 76 Register Symbol Page Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Voltage Monitor 1 Circuit Control Register Voltage Monitor 2 Circuit Control Register Voltage Monitor 0 Circuit Control Register VW1C VW2C VW0C 38 39 37 Voltage Detection Register 1 Voltage Detection Register 2 VCA1 VCA2 36 36, 80 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh INT0 Interrupt Control Register INT0IC 108 Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register TRBIC INT1IC INT3IC 106 108 108 UART0 Transmit Interrupt Control Register S0TIC UART0 Receive Interrupt Control Register UART1 Receive Interrupt Control Register INT2 Interrupt Control Register Timer RA Interrupt Control Register S0RIC S1RIC INT2IC TRAIC UART1 Transmit Interrupt Control Register S1TIC 106 106 106 106 108 106 Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU/IIC Interrupt Control Register KUPIC ADIC SSUIC/IICIC 106 106 107 Timer RD0 Interrupt Control Register Timer RD1 Interrupt Control Register Timer RE Interrupt Control Register TRD0IC TRD1IC TREIC 107 107 106 Register Symbol Page
NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
B-1
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh
Register
Symbol
Page
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h
Register A/D Register
Symbol AD
Page 386
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
386 385 386
UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB
291 291 290 292 293 290 291 291 290 292 293 290
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P4 Direction Register Port P6 Register Port P6 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 PD4 P6 PD6
56 56 56 56 56 56 56 56 56 56 56 56
Port P2 Drive Capacity Control Register UART1 Function Select Register
P2DRR U1SR
58 293
SS Control Register H / IIC bus Control Register 1 SS Control Register L / IIC bus Control Register 2 SS Mode Register / IIC bus Mode Register SS Enable Register / IIC bus Interrupt Enable Register SS Status Register / IIC bus Status Register SS Transmit Data Register/IIC bus Transmit Data Register SS Receive Data Register/IIC bus Receive Data Register
SSCRH/ICCR1 SSCRL/ICCR2 SSMR/ICMR SSER/ICIER SSSR/ICSR SSTDR/ICDRT SSRDR/ICDRR
308, 338 309, 339 310, 340 311, 341 312, 342 313, 343 314, 343 314, 344
00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh
Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1
PMR INTEN INTF KIEN PUR0 PUR1
58, 293, 314, 344 115 116 119 57 57
SS Mode Register 2 / Slave Address Register SSMR2/SAR
NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
B-2
Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh
Register Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register
Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR
Page 135 135, 137, 140, 142, 144, 147 136 136 136 370 371 151 151 152, 154, 158, 160, 165 152 153 153 153
Address 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h 0141h 0142h 0143h
Register
Symbol
Page
Timer RD Start Register Timer RD Mode Register Timer RD PWM Mode Register Timer RD Function Control Register Timer RD Output Master Enable Register 1 Timer RD Output Master Enable Register 2 Timer RD Output Control Register Timer RD Digital Filter Function Select Register 0 Timer RD Digital Filter Function Select Register 1 Timer RD Control Register 0 Timer RD I/O Control Register A0 Timer RD I/O Control Register C0 Timer RD Status Register 0 Timer RD Interrupt Enable Register 0 Timer RD PWM Mode Output Level Control Register 0 Timer RD Counter 0 Timer RD General Register A0 Timer RD General Register B0 Timer RD General Register C0 Timer RD General Register D0 Timer RD Control Register 1 Timer RD I/O Control Register A1 Timer RD I/O Control Register C1 Timer RD Status Register 1 Timer RD Interrupt Enable Register 1 Timer RD PWM Mode Output Level Control Register 1 Timer RD Counter 1 Timer RD General Register A1 Timer RD General Register B1 Timer RD General Register C1 Timer RD General Register D1
TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1 TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1
184, 198, 215, 228, 238, 252 184, 198, 215, 228, 239, 252 185, 199, 216 186, 200, 217, 229, 240, 253 201, 218, 230, 241, 254 201, 218, 230, 241, 254 202, 219, 255 187 187 188, 203, 219, 231, 242, 256 189, 204 190, 205 191, 206, 220, 232, 243, 257 192, 207, 221, 233, 244, 258 222 192, 207, 222, 233, 245, 258 193, 208, 223, 234, 245, 259 193, 208, 223, 234, 245, 259 193, 208, 223, 234, 259 193, 208, 223, 234, 245, 259 188, 203, 219, 242 189, 204 190, 205 191, 206, 220, 232, 243, 257 192, 207, 221, 233, 244, 258 222 192, 207, 222, 245 193, 208, 223, 234, 245, 259 193, 208, 223, 234, 245, 259 193, 208, 223, 234, 245, 259 193, 208, 223, 234, 245, 259
Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register
TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR
273, 281 273, 281
0144h 0145h
274 274 275, 282 276, 282 277, 283 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh
NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
B-3
Address 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh
Register
Symbol
Page
Address 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh FFFFh
Register
Symbol
Page
Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0
FMR4 FMR1 FMR0
408 407 406
Option Function Select Register
OFS
27, 128, 401
NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
B-4
R8C/24 Group, R8C/25 Group
SINGLE-CHIP 16-BIT CMOS MCU
REJ09B0244-0300 Rev.3.00 Feb 29, 2008
1.
Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C/Tiny Series CPU core, and are packaged in a 52-pin molded-plastic LQFP or a 64-pin molded-plastic FLGA. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Furthermore, the R8C/25 Group has on-chip data flash (1 KB x 2 blocks). The difference between the R8C/24 Group and R8C/25 Group is only the presence or absence of data flash. Their peripheral functions are the same.
1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer products, etc.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 1 of 485
R8C/24 Group, R8C/25 Group
1. Overview
1.2
Performance Overview
Table 1.1 outlines the Functions and Specifications for R8C/24 Group and Table 1.2 outlines the Functions and Specifications for R8C/25 Group. Table 1.1 Functions and Specifications for R8C/24 Group Item Specification CPU Number of fundamental 89 instructions instructions Minimum instruction execution 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) time 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.3 Product Information for R8C/24 Group Peripheral Ports I/O ports: 41 pins, Input port: 3 pins Functions LED drive ports I/O ports: 8 pins Timers Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RD: 16 bits x 2 channels (Input capture and output compare circuits) Timer RE: With real-time clock and compare match function Serial interfaces 2 channels (UART0, UART1) Clock synchronous serial I/O, UART Clock synchronous serial 1 channel interface I2C bus Interface(1) Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (timer RA, UART0) A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupts Internal: 11 sources, External: 5 sources, Software: 4 sources, Priority levels: 7 levels Clock Clock generation 3 circuits circuits * XIN clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function * XCIN clock generation circuit (32 kHz) Real-time clock (timer RE) Oscillation stop detection function XIN clock oscillation stop detection function Voltage detection circuit On-chip Power-on reset circuit On-chip Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 2.0 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure endurance 100 times Operating Ambient Temperature -20 to 85C (N version) -40 to 85C (D version)(2) -20 to 105C (Y version)(3) Package 52-pin molded-plastic LQFP 64-pin molded-plastic FLGA
NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D version if D version functions are to be used. 3. Please contact Renesas Technology sales offices for the Y version. Rev.3.00 Feb 29, 2008 REJ09B0244-0300 Page 2 of 485
R8C/24 Group, R8C/25 Group
1. Overview
Table 1.2 CPU
Functions and Specifications for R8C/25 Group
Item Specification Number of fundamental 89 instructions instructions Minimum instruction execution 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) time 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.4 Product Information for R8C/25 Group Peripheral Ports I/O ports: 41 pins, Input port: 3 pins Functions LED drive ports I/O ports: 8 pins Timers Timer RA: 8 bits x 1 channel Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RD: 16 bits x 2 channels (Input capture and output compare circuits) Timer RE: With real-time clock and compare match function Serial interface 2 channels (UART0, UART1) Clock synchronous serial I/O, UART Clock synchronous serial 1 channel interface I2C bus Interface(1) Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (timer RA, UART0) A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupts Internal: 11 sources, External: 5 sources, Software: 4 sources, Priority levels: 7 levels Clock Clock generation 3 circuits circuits * XIN clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function * XCIN clock generation circuit (32 kHz) Real-time clock (timer RE) Oscillation stop detection function XIN clock oscillation stop detection function Voltage detection circuit On-chip Power-on reset circuit On-chip Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 2.0 A (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure 1,0000 times (data flash) endurance 1,000 times (program ROM) Operating Ambient Temperature -20 to 85C (N version) -40 to 85C (D version)(2) -20 to 105C (Y version)(3) Package 52-pin molded-plastic LQFP 64-pin molded-plastic FLGA NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Specify the D version if D version functions are to be used. 3. Please contact Renesas Technology sales offices for the Y version. Rev.3.00 Feb 29, 2008 REJ09B0244-0300 Page 3 of 485
R8C/24 Group, R8C/25 Group
1. Overview
1.3
Block Diagram
Figure 1.1 shows a Block Diagram.
8
8
8
6
3
3
8
I/O ports Peripheral functions
Port P0
Port P1
Port P2
Port P3
Port P4
Port P6
Timers Timer RA (8 bits) Timer RB (8 bits) Timer RD (16 bits x 2 channels) Timer RE (8 bits)
A/D converter (10 bits x 12 channels)
System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator XCIN-XCOUT
UART or clock synchronous serial I/O (8 bits x 2 channels)
I2C bus interface or clock synchronous serial I/O with chip select (8 bits x 1 channel)
LIN module (1 channel)
Watchdog timer (15 bits)
R8C/Tiny Series CPU core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM(1)
RAM(2)
Multiplier
NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type.
Figure 1.1
Block Diagram
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 4 of 485
R8C/24 Group, R8C/25 Group
1. Overview
1.4
Product Information
Table 1.3 lists the Product Information for R8C/24 Group and Table 1.4 lists the Product Information for R8C/25 Group. Table 1.3 Product Information for R8C/24 Group ROM Capacity 16 Kbytes 24 Kbytes 32 Kbytes 48 Kbytes 64 Kbytes 16 Kbytes 32 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 48 Kbytes 64 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 48 Kbytes 64 Kbytes 16 Kbytes 32 Kbytes 16 Kbytes 24 Kbytes 32 Kbytes 48 Kbytes 64 Kbytes RAM Capacity 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes Package Type PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PTLG0064JA-A PTLG0064JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PTLG0064JA-A PTLG0064JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A Current of Feb. 2008 Remarks N version Blank product
Type No. R5F21244SNFP R5F21245SNFP R5F21246SNFP R5F21247SNFP R5F21248SNFP R5F21244SNLG R5F21246SNLG R5F21244SDFP R5F21245SDFP R5F21246SDFP R5F21247SDFP R5F21248SDFP R5F21244SNXXXFP R5F21245SNXXXFP R5F21246SNXXXFP R5F21247SNXXXFP R5F21248SNXXXFP R5F21244SNXXXLG R5F21246SNXXXLG R5F21244SDXXXFP R5F21245SDXXXFP R5F21246SDXXXFP R5F21247SDXXXFP R5F21248SDXXXFP
D version Blank product
N version Factory programming product(1)
D version Factory programming product(1)
NOTE: 1. The user ROM is programmed before shipment.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 5 of 485
R8C/24 Group, R8C/25 Group
1. Overview
Type No.
R 5 F 21 24 6 S N XXX FP
Package type: FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body) LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification N: Operating ambient temperature -20C to 85C D: Operating ambient temperature -40C to 85C Y: Operating ambient temperature -20C to 105C(1) S: Low-voltage version ROM capacity 4: 16 KB 5: 24 KB 6: 32 KB 7: 48 KB 8: 64 KB R8C/24 Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor NOTE: 1. Please contact Renesas Technology sales offices for the Y version.
Figure 1.2
Type Number, Memory Size, and Package of R8C/24 Group
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 6 of 485
R8C/24 Group, R8C/25 Group
1. Overview
Table 1.4
Product Information for R8C/25 Group ROM Capacity Program ROM Data flash 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 48 Kbytes 1 Kbyte x 2 64 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 48 Kbytes 1 Kbyte x 2 64 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 48 Kbytes 1 Kbyte x 2 64 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 24 Kbytes 1 Kbyte x 2 32 Kbytes 1 Kbyte x 2 48 Kbytes 1 Kbyte x 2 64 Kbytes 1 Kbyte x 2 RAM Capacity 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes 1 Kbyte 2 Kbytes 1 Kbyte 2 Kbytes 2 Kbytes 2.5 Kbytes 3 Kbytes
Current of Feb. 2008 Package Type PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PTLG0064JA-A PTLG0064JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PTLG0064JA-A PTLG0064JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A PLQP0052JA-A Remarks N version Blank product
Type No. R5F21254SNFP R5F21255SNFP R5F21256SNFP R5F21257SNFP R5F21258SNFP R5F21254SNLG R5F21256SNLG R5F21254SDFP R5F21255SDFP R5F21256SDFP R5F21257SDFP R5F21258SDFP R5F21254SNXXXFP R5F21255SNXXXFP R5F21256SNXXXFP R5F21257SNXXXFP R5F21258SNXXXFP R5F21254SNXXXLG R5F21256SNXXXLG R5F21254SDXXXFP R5F21255SDXXXFP R5F21256SDXXXFP R5F21257SDXXXFP R5F21258SDXXXFP
D version Blank product
N version Factory programming product(1)
D version Factory programming product(1)
NOTE: 1. The user ROM is programmed before shipment.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 7 of 485
R8C/24 Group, R8C/25 Group
1. Overview
Type No.
R 5 F 21 25 6 S N XXX FP
Package type: FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body) LG: PTLG0064JA-A (0.65 mm pin-pitch, 6 mm square body)
ROM number
Classification N: Operating ambient temperature -20C to 85C D: Operating ambient temperature -40C to 85C Y: Operating ambient temperature -20C to 105C(1) S: Low-voltage version ROM capacity 4: 16 KB 5: 24 KB 6: 32 KB 7: 48 KB 8: 64 KB R8C/25 Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor NOTE: 1. Please contact Renesas Technology sales offices for the Y version.
Figure 1.3
Type Number, Memory Size, and Package of R8C/25 Group
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 8 of 485
R8C/24 Group, R8C/25 Group
1. Overview
1.5
Pin Assignments
Figure 1.4 shows PLQP0052JA-A Package Pin Assignments (Top View). Figure 1.5 shows PTLG0064JA-A Package Pin Assignments.
P6_7/INT3/RXD1
P1_2/KI2/AN10
Pin assignments (top view)
P1_0/KI0/AN8 P1_1/KI1/AN9 P3_0/TRAO P3_1/TRBO P6_5/CLK1 P0_7/AN0
P6_6/INT2/TXD1 28
39
38
37
36
35
34
33
32
31
30
29
NC P0_6/AN1 P0_5/AN2 P0_4/AN3 P4_2/VREF P6_0/TREO P6_2 P6_1 P0_3/AN4 P0_2/AN5 P0_1/AN6 P0_0/AN7 P3_7/SSO
40 41 42 43 44 45 46 47 48 49 50 51 52
10 11 12 13 1 2 3 4 5 6 7 8 9
27
P4_5/INT0
P6_3
P6_4
NC
26 25 24 23 22
NC P1_3/KI3/AN11 P1_4/TXD0 P1_5/RXD0/(TRAIO)/(INT1)(2) P1_6/CLK0 P1_7/TRAIO/INT1 P2_0/TRDIOA0/TRDCLK P2_1/TRDIOB0 P2_2/TRDIOC0 P2_3/TRDIOD0 P2_4/TRDIOA1 P2_5/TRDIOB1 P2_6/TRDIOC1
R8C/24 Group R8C/25 Group
21 20 19 18 17 16 15 14
P3_3/SSI
P3_5/SCL/SSCK
P3_4/SDA/SCS
NOTES: 1. P4_7 is an input-only port. 2. Can be assigned to the pin in parentheses by a program. NC: Non-Connection
Package: PLQP0052JA-A(52P6A-A) 0.65 mm pin pitch, 10 mm square body
Figure 1.4
PLQP0052JA-A Package Pin Assignments (Top View)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 9 of 485
P2_7/TRDIOD1
XOUT/P4_7
MODE
P4_4/XCOUT
VSS/AVSS
RESET
P4_6/XIN
(1)
VCC/AVCC
NC
P4_3/XCIN
R8C/24 Group, R8C/25 Group
1. Overview
Pin assignments (top perspective view) A B C D E F G H
8
3
P3_3/SSI
50
P0_1/AN6
48
P0_3/AN4
46
P6_2
45
P6_0/TREO
NC
36
P6_4
NC
8
7
4
P3_4/SDA/ SCS
51
P0_0/AN7
49
P0_2/AN5
NC
44 43
P0_4/AN3
34 42
P0_5/AN2
35
NC
NC
P4_2/VREF P3_0/TRAO P6_5/CLK1
7
6
NC
5
MODE
52
P3_7/SSO
47
P6_1
33
P3_1/TRBO
6
5
7
P4_4/XCOUT
NC
6
P4_3/XCIN
2
P3_5/SCL/ SSCK
37
P6_3
NC
41
P0_6/AN1
38
P0_7/AN0
5
4
13
P2_7/ TRDIOD1
12
VCC/AVCC
NC
9
XOUT/ P4_7(1)
8
RESET
32
P1_0/KI0/ AN8
31
P1_1/KI1/ AN9
NC
4
3
NC
10
VSS/AVSS
16
P2_4/ TRDIOA1
19 20 21
23
NC
NC
NC
30
P1_2/KI2/ AN10
P1_5/RXD0/ P2_1/ TRDIOB0 (TRAIO)/(INT1)(2)
3
2
NC
11
XIN/P4_6
17 18
24
P1_4/TXD0
28
P6_6/INT2/ TXD1
NC
P2_3/ P2_0/TRDIOA0/ TRDIOD0 TRDCLK
2
1
14
P2_6/ TRDIOC1
15
P2_5/ TRDIOB1
22
25
P1_3/KI3/ AN11
27
P4_5/INT0
29
P6_7/INT3/ RXD1
P2_2/ P1_7/TRAIO/ P1_6/CLK0 TRDIOC0 INT1
1
A
B
C
D
E
F
G
H
Package: PTLG0064JA-A(64F0G) 0.65 mm pin pitch, 6 mm square body NOTES: 1. P4_7 is an input-only port. 2. Can be assigned to the pin in parentheses by a program. 3. In the figure, the numbers in circles are the pin numbers of the 52-pin LQFP package (PLQP0052JA-A). NC: Non-Connection R5F21244S NLG JAPAN
Pin assignments (top view)
Figure 1.5
PTLG0064JA-A Package Pin Assignments Page 10 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
1. Overview
1.6
Pin Functions
Table 1.5 lists Pin Functions. Table 1.5
Type Power supply input Analog power supply input Reset input MODE XIN clock input XIN clock output XCIN clock input XCIN clock output INT interrupt input Key input interrupt Timer RA Timer RB Timer RD
Pin Functions
Symbol VCC, VSS AVCC, AVSS RESET MODE XIN XOUT XCIN XCOUT INT0 to INT3 KI0 to KI3 TRAIO TRAO TRBO TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TRDCLK TREO CLK0, CLK1 RXD0, RXD1 TXD0, TXD1 I/O Type I I I I I O I O I I I/O O O I/O Description Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave the XOUT pin open. These pins are provided for XCIN clock generation circuit I/O. Connect a crystal oscillator between the XCIN and XCOUT pins. To use an external clock, input it to the XCIN pin and leave the XCOUT pin open. INT interrupt input pins. INT0 is timer RD input pin. INT1 is timer RA input pin. Key input interrupt input pins Timer RA I/O pin Timer RA output pin Timer RB output pin Timer RD I/O ports
I O I/O I O I/O I/O I/O I/O I/O I/O I I I/O
External clock input pin Divided clock output pin Transfer clock I/O pin Serial data input pins Serial data output pins Clock I/O pin Data I/O pin Data I/O pin Chip-select signal I/O pin Clock I/O pin Data I/O pin Reference voltage input pin to A/D converter Analog input pins to A/D converter CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. P2_0 to P2_7 also function as LED drive ports. Input-only ports
Timer RE Serial interface
I2C
bus interface
SCL SDA SSI SCS SSCK SSO VREF AN0 to AN11 P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, P6_0 to P6_7 P4_2, P4_6, P4_7
Clock synchronous serial I/O with chip select
Reference voltage input A/D converter I/O port
Input port I: Input
I
O: Output
I/O: Input and output
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 11 of 485
R8C/24 Group, R8C/25 Group
1. Overview
Table 1.6
Pin Name Information by Pin Number
I/O Pin Functions for of Peripheral Modules Clock Serial Synchronous I2C bus Timer Interface Serial I/O with Interface Chip Select SSCK SCL SSI SCS SDA
Pin Control Pin Number 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 35 36 37 38 41 42 43 44 45 46 47 48 49 50 51 52
Port
Interrupt
A/D Converter
P3_5 P3_3 P3_4 MODE XCIN XCOUT RESET XOUT VSS/AVSS XIN VCC/AVCC P4_3 P4_4 P4_7 P4_6 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P4_5 P6_6 P6_7 P1_2 P1_1 P1_0 P3_1 P3_0 P6_5 P6_4 P6_3 P0_7 P0_6 P0_5 P0_4 P4_2 P6_0 P6_2 P6_1 P0_3 P0_2 P0_1 P0_0 P3_7
INT1 (INT1)(1) KI3 INT0 INT2 INT3 KI2 KI1 KI0
TRDIOD1 TRDIOC1 TRDIOB1 TRDIOA1 TRDIOD0 TRDIOC0 TRDIOB0 TRDIOA0/TRDCLK TRAIO (TRAIO)(1) CLK0 RXD0 TXD0 AN11 INT0 TXD1 RXD1 AN10 AN9 AN8 TRBO TRAO CLK1
AN0 AN1 AN2 AN3 TREO
VREF
AN4 AN5 AN6 AN7 SSO
NOTE: 1. Can be assigned to the pin in parentheses by a program.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 12 of 485
R8C/24 Group, R8C/25 Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R2 R3
R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1)
R2 R3 A0 A1 FB
b19 b15 b0
Address registers(1) Frame base register(1)
INTBH
INTBL
Interrupt table register
The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL.
b19 b0
PC
Program counter
b15
b0
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit
NOTE: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 13 of 485
R8C/24 Group, R8C/25 Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 14 of 485
R8C/24 Group, R8C/25 Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 15 of 485
R8C/24 Group, R8C/25 Group
3. Memory
3.
3.1
Memory
R8C/24 Group
Figure 3.1 is a Memory Map of R8C/24 Group. The R8C/24 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte internal RAM area is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXh 0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
Internal ROM (program ROM)
0FFFFh 1ZZZZh FFFFFh
Internal ROM (program ROM)
0FFFFh
(Reserved) (Reserved) Reset
NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F21244SNFP, R5F21244SNXXXFP, R5F21244SDFP, R5F21244SDXXXFP, R5F21244SNLG, R5F21244SNXXXLG R5F21245SNFP, R5F21245SNXXXFP, R5F21245SDFP, R5F21245SDXXXFP R5F21246SNFP, R5F21246SNXXXFP, R5F21246SDFP, R5F21246SDXXXFP, R5F21246SNLG, R5F21246SNXXXLG R5F21247SNFP, R5F21247SNXXXFP, R5F21247SDFP, R5F21247SDXXXFP R5F21248SNFP, R5F21248SNXXXFP, R5F21248SDFP, R5F21248SDXXXFP Size 16 Kbytes Address 0YYYYh 0C000h Address 1ZZZZh - - - - 13FFFh Size 1 Kbyte Internal RAM Address 0XXXXh 007FFh
24 Kbytes 32 Kbytes
0A000h 08000h
2 Kbytes 2 Kbytes
00BFFh 00BFFh
48 Kbytes 64 Kbytes
04000h 04000h
2.5 Kbytes 3 Kbytes
00DFFh 00FFFh
Figure 3.1
Memory Map of R8C/24 Group Page 16 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
3. Memory
3.2
R8C/25 Group
Figure 3.2 is a Memory Map of R8C/25 Group. The R8C/25 group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte internal RAM is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special Function Registers (SFRs))
002FFh
00400h
Internal RAM
0XXXXh 02400h
Internal ROM (data flash)(1)
02BFFh
0FFDCh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer/oscillation stop detection/voltage monitor
0YYYYh
Internal ROM (program ROM)
0FFFFh 1ZZZZh FFFFFh
Internal ROM (program ROM)
0FFFFh
(Reserved) (Reserved) Reset
NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number R5F21254SNFP, R5F21254SNXXXFP, R5F21254SDFP, R5F21254SDXXXFP, R5F21254SNLG, R5F21254SNXXXLG R5F21255SNFP, R5F21255SNXXXFP, R5F21255SDFP, R5F21255SDXXXFP R5F21256SNFP, R5F21256SNXXXFP, R5F21256SDFP, R5F21256SDXXXFP, R5F21256SNLG, R5F21256SNXXXLG R5F21257SNFP, R5F21257SNXXXFP, R5F21257SDFP, R5F21257SDXXXFP R5F21258SNFP, R5F21258SNXXXFP, R5F21258SDFP, R5F21258SDXXXFP Size 16 Kbytes Address 0YYYYh 0C000h Address 1ZZZZh - - - - 13FFFh Size 1 Kbyte Internal RAM Address 0XXXXh 007FFh
24 Kbytes 32 Kbytes
0A000h 08000h
2 Kbytes 2 Kbytes
00BFFh 00BFFh
48 Kbytes 64 Kbytes
04000h 04000h
2.5 Kbytes 3 Kbytes
00DFFh 00FFFh
Figure 3.2
Memory Map of R8C/25 Group
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 17 of 485
R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Eh 003Fh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1 and hardware reset. 4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset. 5. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3. 6. The CSPROINI bit in the OFS register is set to 0.
SFR Information (1)(1)
Register Symbol After reset
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1
PM0 PM1 CM0 CM1
00h 00h 01101000b 00100000b
Protect Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0
PRCR OCD WDTR WDTS WDC RMAD0
00h 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h
Address Match Interrupt Enable Register Address Match Interrupt Register 1
AIER RMAD1
Count Source Protection Mode Register
CSPR
00h 10000000b(6)
High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2
FRA0 FRA1 FRA2
00h When shipping 00h
Clock Prescaler Reset Flag High-Speed On-Chip Oscillator Control Register 4 High-Speed On-Chip Oscillator Control Register 6 High-Speed On-Chip Oscillator Control Register 7
CPSRF FRA4 FRA6 FRA7
00h When shipping When shipping When shipping
Voltage Detection Register 1(2) Voltage Detection Register 2(2)
VCA1 VCA2
00001000b 00h(3) 00100000b(4)
Voltage Monitor 1 Circuit Control Register(5) Voltage Monitor 2 Circuit Control Register(5) Voltage Monitor 0 Circuit Control Register(2)
VW1C VW2C VW0C
00001000b 00h 0000X000b(3) 0100X001b(4)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 18 of 485
R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.2
Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh
SFR Information (2)(1)
Register Symbol After reset
Timer RD0 Interrupt Control Register Timer RD1 Interrupt Control Register Timer RE Interrupt Control Register
TRD0IC TRD1IC TREIC
XXXXX000b XXXXX000b XXXXX000b
Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU/IIC Interrupt Control Register(2) UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register INT2 Interrupt Control Register Timer RA Interrupt Control Register Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register
KUPIC ADIC SSUIC / IICIC S0TIC S0RIC S1TIC S1RIC INT2IC TRAIC TRBIC INT1IC INT3IC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b XXXXX000b XX00X000b XX00X000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 19 of 485
R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.3
Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh
SFR Information (3)(1)
Register Symbol After reset
UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register
U0MR U0BRG U0TB U0C0 U0C1 U0RB U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh
SS Control Register H / IIC bus Control Register 1(2) SS Control Register L / IIC bus Control Register 2(2) SS Mode Register / IIC bus Mode Register(2) SS Enable Register / IIC bus Interrupt Enable Register(2) SS Status Register / IIC bus Status Register(2) SS Mode Register 2 / Slave Address Register(2) SS Transmit Data Register / IIC bus Transmit Data Register(2) SS Receive Data Register / IIC bus Receive Data Register(2)
SSCRH / ICCR1 SSCRL / ICCR2 SSMR / ICMR SSER / ICIER SSSR / ICSR SSMR2 / SAR SSTDR / ICDRT SSRDR / ICDRR
00h 01111101b 00011000b 00h 00h / 0000X000b 00h FFh FFh
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 20 of 485
R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.4
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh
SFR Information (4)(1)
Register A/D Register AD Symbol XXh XXh After reset
A/D Control Register 2 A/D Control Register 0 A/D Control Register 1
ADCON2 ADCON0 ADCON1
00h 00h 00h
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P4 Direction Register Port P6 Register Port P6 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 PD4 P6 PD6
XXh XXh 00h 00h XXh XXh 00h 00h XXh 00h XXh 00h
Port P2 Drive Capacity Control Register UART1 Function Select Register
P2DRR U1SR
00h XXh
Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1
PMR INTEN INTF KIEN PUR0 PUR1
00h 00h 00h 00h 00h XX00XX00b
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 21 of 485
R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.5
Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh
SFR Information (5)(1)
Register Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h FFh FFh FFh
Timer RE Second Data Register / Counter Data Register Timer RE Minute Data Register / Compare Data Register Timer RE Hour Data Register Timer RE Day of Week Data Register Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register
TRESEC TREMIN TREHR TREWK TRECR1 TRECR2 TRECSR
00h 00h 00h 00h 00h 00h 00001000b
Timer RD Start Register Timer RD Mode Register Timer RD PWM Mode Register Timer RD Function Control Register Timer RD Output Master Enable Register 1 Timer RD Output Master Enable Register 2 Timer RD Output Control Register Timer RD Digital Filter Function Select Register 0 Timer RD Digital Filter Function Select Register 1
TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1
11111100b 00001110b 10001000b 10000000b FFh 01111111b 00h 00h 00h
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 22 of 485
R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.6
Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh
SFR Information (6)(1)
Register Timer RD Control Register 0 Timer RD I/O Control Register A0 Timer RD I/O Control Register C0 Timer RD Status Register 0 Timer RD Interrupt Enable Register 0 Timer RD PWM Mode Output Level Control Register 0 Timer RD Counter 0 Timer RD General Register A0 Timer RD General Register B0 Timer RD General Register C0 Timer RD General Register D0 Timer RD Control Register 1 Timer RD I/O Control Register A1 Timer RD I/O Control Register C1 Timer RD Status Register 1 Timer RD Interrupt Enable Register 1 Timer RD PWM Mode Output Level Control Register 1 Timer RD Counter 1 Timer RD General Register A1 Timer RD General Register B1 Timer RD General Register C1 Timer RD General Register D1 Symbol TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 After reset 00h 10001000b 10001000b 11100000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h 10001000b 10001000b 11000000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh
X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 23 of 485
R8C/24 Group, R8C/25 Group
4. Special Function Registers (SFRs)
Table 4.7
Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FFFFh
SFR Information (7)(1)
Register Symbol After reset
Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0
FMR4 FMR1 FMR0
01000000b 1000000Xb 00000001b
Option Function Select Register
OFS
(Note 2)
X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 24 of 485
R8C/24 Group, R8C/25 Group
5. Resets
5.
Resets
The following resets are implemented: hardware reset, power-on reset, voltage monitor 0 reset, voltage monitor 1 reset, voltage monitor 2 reset, watchdog timer reset, and software reset. Table 5.1 lists the Reset Names and Sources. Table 5.1 Reset Names and Sources Reset Name Hardware reset Power-on reset Voltage monitor 0 reset Voltage monitor 1 reset Voltage monitor 2 reset Watchdog timer reset Software reset Source Input voltage of RESET pin is held "L" VCC rises VCC falls (monitor voltage: Vdet0) VCC falls (monitor voltage: Vdet1) VCC falls (monitor voltage: Vdet2) Underflow of watchdog timer Write 1 to PM03 bit in PM0 register
RESET
Hardware reset
SFRs
Bits VCA25, VW0C0, and VW0C6
SFRs VCC Power-on reset circuit
Power-on reset Bits VCA25, VW0C0, and VW0C6
Voltage monitor 0 reset
SFRs
Bits VCA13, VCA26, VCA27, VW1C2, VW1C3, VW2C2, VW2C3, VW0C1, VW0F0, VW0F1, and VW0C7
Voltage detection circuit
Voltage monitor 1 reset
Voltage monitor 2 reset Watchdog timer reset
Watchdog timer
CPU
Pin, CPU, and SFR bits other than those listed above
Software reset
VCA13: Bit in VCA1 register VCA25, VCA26, VCA27: Bits in VCA2 register VW0C0, VW0C1, VW0C6, VW0F0, VW0F1, VW0C7: Bits in VW0C register VW1C2, VW1C3: Bits in VW1C register VW2C2, VW2C3: Bits in VW2C register
Figure 5.1
Block Diagram of Reset Circuit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 25 of 485
R8C/24 Group, R8C/25 Group
5. Resets
Table 5.2 shows the Pin Functions while RESET Pin Level is "L", Figure 5.2 shows the CPU Register Status after Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register. Table 5.2 Pin Functions while RESET Pin Level is "L" Pin Name P0, P1, P2 P3_0, P3_1, P3_3 to P3_5, P3_7 P4_2 to P4_7 P6 Input port Input port Input port Input port Pin Functions
b15
b0
0000h 0000h 0000h 0000h 0000h 0000h 0000h
b19 b0
Data register(R0) Data register(R1) Data register(R2) Data register(R3) Address register(A0) Address register(A1) Frame base register(FB)
00000h Content of addresses 0FFFEh to 0FFFCh
b15 b0
Interrupt table register(INTB) Program counter(PC)
0000h 0000h 0000h
b15 b0
User stack pointer(USP) Interrupt stack pointer(ISP) Static base register(SB)
0000h
b15 b8 b7 b0
Flag register(FLG)
IPL
Figure 5.2
U I OBSZDC
CPU Register Status after Reset
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 26 of 485
R8C/24 Group, R8C/25 Group
5. Resets
fOCO-S
RESET pin 10 cycles or more are needed(1) fOCO-S clock x 32 cycles(2) Internal reset signal Start time of flash memory (CPU clock x 14 cycles) CPU clock x 28 cycles
CPU clock 0FFFCh Address (internal address signal) 0FFFDh Content of reset vector 0FFFEh
NOTES: 1. Hardware reset. 2. When the "L" input width to the RESET pin is set to fOCO-S clock x 32 cycles or more, setting the RESET pin to "H" also sets the internal reset signal to "H" at the same.
Figure 5.3
Reset Sequence
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol OFS Bit Symbol WDTON -- (b1) ROMCR ROMCP1 -- (b4)
Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Voltage detection 0 circuit start bit(2)
When Shipping FFh(3) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. 0 : Voltage monitor 0 reset enabled after hardw are reset 1 : Voltage monitor 0 reset disabled after hardw are reset Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset
RW RW RW RW RW RW
LVD0ON
RW
-- (b6)
Reserved bit
RW
Count source protect CSPROINI mode after reset select bit
RW
NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after reset). 3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 5.4
OFS Register Page 27 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
5. Resets
5.1
Hardware Reset
A reset is applied using the RESET pin. When an "L" signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions while RESET Pin Level is "L"). When the input level applied to the RESET pin changes from "L" to "H", a program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset. The internal RAM is not reset. If the RESET pin is pulled "L" while writing to the internal RAM is in progress, the contents of internal RAM will be undefined. Figure 5.5 shows an Example of Hardware Reset Circuit and Operation and Figure 5.6 shows an Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
5.1.1
When Power Supply is Stable
(1) Apply "L" to the RESET pin. (2) Wait for 10 s or more. (3) Apply "H" to the RESET pin.
5.1.2
Power On
(1) Apply "L" to the RESET pin. (2) Let the supply voltage increase until it meets the recommended operating conditions. (3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 20. Electrical Characteristics). (4) Wait for 10 s or more. (5) Apply "H" to the RESET pin.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 28 of 485
R8C/24 Group, R8C/25 Group
5. Resets
VCC VCC 0V RESET RESET
2.2 V
0.2 VCC or below 0V td(P-R) + 10 s or more
NOTE:
1. Refer to 20. Electrical Characteristics.
Figure 5.5
Example of Hardware Reset Circuit and Operation
Supply voltage detection circuit
5V VCC 2.2 V
RESET
VCC 0V 5V RESET
0V td(P-R) + 10 s or more Example when VCC = 5 V NOTE: 1. Refer to 20. Electrical Characteristics.
Figure 5.6
Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 29 of 485
R8C/24 Group, R8C/25 Group
5. Resets
5.2
Power-On Reset Function
When the RESET pin is connected to the VCC pin via a pull-up resistor, and the VCC pin voltage level rises while the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR. When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more. When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held "H" and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock after reset. Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset. The voltage monitor 0 reset is enabled after power-on reset. Figure 5.7 shows an Example of Power-On Reset Circuit and Operation.
VCC 4.7 k (reference) RESET
Vdet0(3) 2.2V External Power VCC Vpor1 tw(por1) Sampling time(1, 2) trth Vpor2 trth
Vdet0(3)
Internal reset signal ("L" valid) 1 x 32 fOCO-S 1 x 32 fOCO-S
NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. 4. Refer to 20. Electrical Characteristics. 5. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
Figure 5.7
Example of Power-On Reset Circuit and Operation
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 30 of 485
R8C/24 Group, R8C/25 Group
5. Resets
5.3
Voltage Monitor 0 Reset
A reset is applied using the on-chip voltage detection 0 circuit. The voltage detection 0 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet0. When the input voltage to the VCC pin reaches the Vdet0 level or below, the pins, CPU, and SFR are reset. When the input voltage to the VCC pin reaches the Vdet0 level or above, the low-speed on-chip oscillator clock start counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held "H" and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock after reset. The LVD0ON bit in the OFS register can be used to enable or disable voltage monitor 0 reset after a hardware reset. Setting the LVD0ON bit is only valid after a hardware reset. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. The LVD0ON bit cannot be changed by a program. To set the LVD0ON bit, write 0 (voltage monitor 0 reset enabled after hardware reset) or 1 (voltage monitor 0 reset disabled after hardware reset) to bit 5 of address 0FFFFh using a flash programmer. Refer to Figure 5.4 OFS Register for details of the OFS register. Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 0 reset. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet0 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 0 reset.
5.4
Voltage Monitor 1 Reset
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet1. When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are reset and a program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.5
Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input voltage to the VCC pin. The voltage to monitor is Vdet2. When the input voltage to the VCC pin reaches the Vdet2 level or below, the pins, CPU, and SFR are reset and the program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while writing to the internal RAM is in progress, the contents of internal RAM are undefined. Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 31 of 485
R8C/24 Group, R8C/25 Group
5. Resets
5.6
Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins, CPU, and SFR if the watchdog timer underflows. Then the program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock. The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are undefined. Refer to 13. Watchdog Timer for details of the watchdog timer.
5.7
Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected for the CPU clock. The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details. The internal RAM is not reset.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 32 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
6.
Voltage Detection Circuit
The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor the VCC input voltage by a program. Alternately, voltage monitor 0 reset, voltage monitor 1 interrupt, voltage monitor 1 reset, voltage monitor 2 interrupt, and voltage monitor 2 reset can also be used. Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.4 show the Block Diagrams. Figures 6.5 to 6.8 show the Associated Registers. Table 6.1
VCC Monitor
Specifications of Voltage Detection Circuit
Item Voltage to monitor Detection target Voltage Detection 0 Vdet0 Whether passing through Vdet0 by rising or falling None Voltage Detection 1 Voltage Detection 2 Vdet1 Vdet2 Passing through Vdet1 by Passing through Vdet2 by rising or falling rising or falling VW1C3 bit in VW1C register Whether VCC is higher or lower than Vdet1 Voltage monitor 1 reset Reset at Vdet1 > VCC; restart CPU operation after a specified time Voltage monitor 1 interrupt Interrupt request at Vdet1 > VCC and VCC > Vdet1 when digital filter is enabled; interrupt request at Vdet1 > VCC or VCC > Vdet1 when digital filter is disabled Available VCA13 bit in VCA1 register Whether VCC is higher or lower than Vdet2 Voltage monitor 2 reset Reset at Vdet2 > VCC; restart CPU operation after a specified time Voltage monitor 2 interrupt Interrupt request at Vdet2 > VCC and VCC > Vdet2 when digital filter is enabled; interrupt request at Vdet2 > VCC or VCC > Vdet2 when digital filter is disabled Available (Divide-by-n of fOCO-S) x4 n: 1, 2, 4, and 8
Monitor
Process Reset When Voltage is Detected Interrupt
Voltage monitor 0 reset Reset at Vdet0 > VCC; restart CPU operation at VCC > Vdet0 None
Digital Filter
Switch enabled/disabled Sampling time
Available
(Divide-by-n of fOCO-S) (Divide-by-n of fOCO-S) x4 x4 n: 1, 2, 4, and 8 n: 1, 2, 4, and 8
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 33 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
VCC
VCA27
+
Internal reference voltage
Noise filter
Vdet2
Voltage detection 2 signal
-
VCA1 register
b3
VCA26
VCA13 bit
+ -
Noise filter
Vdet1
Voltage detection 1 signal
VW1C register
b3
VCA25
VW1C3 bit
+ -
Voltage detection 0 signal Vdet0
Figure 6.1
Block Diagram of Voltage Detection Circuit
Voltage monitor 0 reset generation circuit
VW0F1 to VW0F0 = 00b = 01b
Voltage detection 0 circuit
fOCO-S VCA25
= 10b
1/2
1/2
1/2
= 11b
VW0C1 VCC Internal reference voltage + Voltage detection 0 signal Voltage detection 0 signal is held "H" when VCA25 bit is set to 0 (disabled)
Digital filter
VW0C1
Voltage monitor 0 reset signal
VW0C0 VW0C7 VW0C6
VW0C0 to VW0C1, VW0F0 to VW0F1, VW0C6, VW0C7: Bits in VW0C register VCA25: Bit in VCA2 register
Figure 6.2
Block Diagram of Voltage Monitor 0 Reset Generation Circuit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 34 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
Voltage monitor 1 interrupt/reset generation circuit
VW1F1 to VW1F0 = 00b = 01b
Voltage detection 1 circuit
fOCO-S VCA26 VW1C3 VCC Internal reference voltage + Noise filter (Filter width: 200 ns) Voltage detection 1 signal
= 10b
1/2
1/2
1/2
= 11b
VW1C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA26 bit is set to 0 (voltage detection 1 circuit disabled), VW1C2 bit is set to 0 VW1C1 Watchdog timer interrupt signal VW1C2
Digital filter
Voltage detection 1 signal is held "H" when VCA26 bit is set to 0 (disabled) VW1C1
Voltage monitor 1 interrupt signal
Non-maskable interrupt signal
Oscillation stop detection interrupt signal VW1C7 VW1C0 VW1C6
Voltage monitor 1 reset signal
VW1C0 to VW1C3, VW1F0, VW1F1, VW1C6, VW1C7: Bits in VW1C register VCA26: Bit in VCA2 register
Figure 6.3
Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit
Voltage monitor 2 interrupt/reset generation circuit
VW2F1 to VW2F0 = 00b = 01b
Voltage detection 2 circuit
fOCO-S VCA27 VCA13 VCC Internal reference voltage + Noise filter (Filter width: 200 ns) Voltage detection 2 signal
= 10b
1/2
1/2
1/2
= 11b
VW2C2 bit is set to 0 (not detected) by writing 0 by a program. When VCA27 bit is set to 0 (voltage detection 2 circuit disabled), VW2C2 bit is set to 0 VW2C1 Digital filter Watchdog timer interrupt signal VW2C2
Voltage detection 2 signal is held "H" when VCA27 bit is set to 0 (disabled) VW2C1
Voltage monitor 2 interrupt signal
Non-maskable interrupt signal
Watchdog timer block VW2C3 VW2C7 Watchdog timer underflow signal VW2C0 VW2C6
Oscillation stop detection interrupt signal
This bit is set to 0 (not detected) by writing 0 by a program.
Voltage monitor 2 reset signal
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register VCA13: Bit in VCA1 register VCA27: Bit in VCA2 register
Figure 6.4
Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 35 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
Voltage Detection Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0000
000
Symbol Address 0031h VCA1 Bit Symbol Bit Name Reserved bits -- (b2-b0) VCA13 -- (b7-b4) Voltage detection 2 signal monitor flag(1) Reserved bits
After Reset(2) 00001000b Function Set to 0. 0 : VCC < Vdet2 1 : VCC Vdet2 or voltage detection 2 circuit disabled Set to 0.
RW RW
RO
RW
NOTES: 1. The VCA13 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). The VCA13 bit is set to 1 (VCC Vdet 2) w hen the VCA27 bit in the VCA2 register is set to 0 (voltage detection 2 circuit disabled). 2. The softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register.
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol
Address
VCA2 Bit Symbol VCA20 -- (b4-b1) VCA25 VCA26 VCA27
0032h Bit Name Internal pow er low consumption enable bit(6) Reserved bits Voltage detection 0 enable bit(2) Voltage detection 1 enable bit(3) Voltage detection 2 enable bit(4)
After Reset(5) The LVD0ON bit in the OFS register is set to 1 and hardw are reset : 00h Pow er-on reset, voltage monitor 0 reset or LVD0ON bit in the OFS register is set to 0, and hardw are reset : 00100000b Function 0 : Disables low consumption 1 : Enables low consumption Set to 0. 0 : Voltage detection 0 circuit disabled 1 : Voltage detection 0 circuit enabled 0 : Voltage detection 1 circuit disabled 1 : Voltage detection 1 circuit enabled 0 : Voltage detection 2 circuit disabled 1 : Voltage detection 2 circuit enabled RW RW RW RW RW RW
NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register. 2. To use the voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. 6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure 10.9 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 6.5
Registers VCA1 and VCA2 Page 36 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
Voltage Monitor 0 Circuit Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
Address
After Reset(2) The LVD0ON bit in the OFS register is set to 1 and hardw are reset : 0000X000b Pow er-on reset, voltage monitor 0 reset or LVD0ON bit in the OFS register is set to 0, and hardw are reset : 0100X001b Function 0 : Disable 1 : Enable RW RW
VW0C Bit Symbol VW0C0
0038h Bit Name Voltage monitor 0 reset enable bit(3)
VW0C1
Voltage monitor 0 digital filter 0 : Digital filter enabled mode disable mode select bit (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) Reserved bit Reserved bit Sampling clock select bits Set to 0. When read, the content is undefined.
b5 b4
RW
VW0C2 -- (b3) VW0F0
RW RO RW
VW0F1 Voltage monitor 0 circuit mode select bit Voltage monitor 0 reset generation condition select bit(4)
0 0 : fOCO-S divided by 0 1 : fOCO-S divided by 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by
1 2 4 8
RW
VW0C6
When the VW0C0 bit is set to 1 (voltage monitor 0 reset enabled), set to 1. When the VW0C1 bit is set to 1 (digital filter disabled mode), set to 1.
RW
VW0C7
RW
NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW0C register. 2. The value remains unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset. 3. The VW0C0 bit is enabled w hen the VCA25 bit in the VCA2 register is set to 1 (voltage detection 0 circuit enabled). Set the VW0C0 bit to 0 (disable), w hen the VCA25 bit is set to 0 (voltage detection 0 circuit disabled). 4. The VW0C7 bit is enabled w hen the VW0C1 bit set to 1 (digital filter disabled mode).
Figure 6.6
VW0C Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 37 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
Voltage Monitor 1 Circuit Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol VW1C Bit Symbol VW1C0
Address 0036h Bit Name Voltage monitor 1 interrupt/reset enable bit(6) Voltage monitor 1 digital filter disable mode select bit(2)
After Reset(8) 00001000b Function 0 : Disable 1 : Enable 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) 0 : Not detected 1 : Vdet1 crossing detected
RW RW
VW1C1
RW
VW1C2
Voltage change detection flag(3, 4, 8)
RW
VW1C3
Voltage detection 1 signal monitor 0 : VCC < Vdet1 1 : VCC Vdet1 or voltage detection 1 flag(3, 8) circuit disabled Sampling clock select bits
b5 b4
RO
VW1F0
VW1F1 VW1C6 Voltage monitor 1 circuit mode select bit(5) Voltage monitor 1 interrupt/reset generation condition select bit(7, 9)
0 0 : fOCO-S divided by 0 1 : fOCO-S divided by 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by
1 2 4 8
RW
RW RW
0 : Voltage monitor 1 interrupt mode 1 : Voltage monitor 1 reset mode 0 : When VCC reaches Vdet1 or above 1 : When VCC reaches Vdet1 or below
VW1C7
RW
NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (rew rite enable) before w riting to the VW1C register. 2. To use the voltage monitor 1 interrupt to exit stop mode and to return again, w rite 0 to the VW1C1 bit before w riting 1. 3. Bits VW1C2 and VW1C3 are enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). 4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). 5. The VW1C6 bit is enabled w hen the VW1C0 bit is set to 1 (voltage monitor 1 interrupt/enabled reset). 6. The VW1C0 bit is enabled w hen the VCA26 bit in the VCA2 register is set to 1 (voltage detection 1 circuit enabled). Set the VW1C0 bit to 0 (disable) w hen the VCA26 bit is set to 0 (voltage detection 1 circuit disabled). 7. The VW1C7 bit is enabled w hen the VW1C1 bit is set to 1 (digital filter disabled mode). 8. Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset. 9. When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (w hen VCC reaches Vdet1 or below ). (Do not set to 0.)
Figure 6.7
VW1C Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 38 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
Voltage Monitor 2 Circuit Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol VW2C Bit Symbol VW2C0
Address 0037h Bit Name Voltage monitor 2 interrupt/reset enable bit(6) Voltage monitor 2 digital filter disable mode select bit(2)
After Reset(8) 00h Function 0 : Disable 1 : Enable 0 : Digital filter enabled mode (digital filter circuit enabled) 1 : Digital filter disabled mode (digital filter circuit disabled) 0 : Not detected 1 : VCC has crossed Vdet2 0 : Not detected 1 : Detected
b5 b4
RW RW
VW2C1
RW
VW2C2 VW2C3 VW2F0
Voltage change detection flag(3, 4, 8) WDT detection flag(4, 8) Sampling clock select bits
RW RW RW
VW2F1 VW2C6 Voltage monitor 2 circuit mode select bit(5) Voltage monitor 2 interrupt/reset generation condition select bit(7, 9)
0 0 : fOCO-S divided by 0 1 : fOCO-S divided by 1 0 : fOCO-S divided by 1 1 : fOCO-S divided by
1 2 4 8
RW RW
0 : Voltage monitor 2 interrupt mode 1 : Voltage monitor 2 reset mode 0 : When VCC reaches Vdet2 or above 1 : When VCC reaches Vdet2 or below
VW2C7
RW
NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VW2C register. 2. To use the voltage monitor 2 interrupt to exit stop mode and to return again, w rite 0 to the VW2C1 bit before w riting 1. 3. The VW2C2 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). 4. Set this bit to 0 by a program. When 0 is w ritten by a program, it is set to 0 (and remains unchanged even if 1 is w ritten to it). 5. The VW2C6 bit is enabled w hen the VW2C0 bit is set to 1 (voltage monitor 2 interrupt/enables reset). 6. The VW2C0 bit is enabled w hen the VCA27 bit in the VCA2 register is set to 1 (voltage detection 2 circuit enabled). Set the VW2C0 bit to 0 (disable) w hen the VCA27 bit is set to 0 (voltage detection 2 circuit disabled). 7. The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 (digital filter disabled mode). 8. Bits VW2C2 and VW2C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset. 9. When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (w hen VCC reaches Vdet2 or below ). (Do not set to 0.)
Figure 6.8
VW2C Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 39 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
6.1 6.1.1
VCC Input Voltage Monitoring Vdet0
Vdet0 cannot be monitored.
6.1.2
Monitoring Vdet1
Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled). After td(E-A) has elapsed (refer to 20. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW1C register.
6.1.3
Monitoring Vdet2
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has elapsed (refer to 20. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA1 register.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 40 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
6.2
Voltage Monitor 0 Reset
Table 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor Reset and Figure 6.9 shows an Example of Voltage Monitor 0 Reset Operation. To use the voltage monitor 0 reset to exit stop mode, set the VW0C1 bit in the VW0C register to 1 (digital filter disabled). Table 6.2 Step 1 2 3 4(1) 5(1) 6 7 8 9 Procedure for Setting Bits Associated with Voltage Monitor Reset When Using Digital Filter When Not Using Digital Filter Set the VCA25 bit in the VCA2 register to 1 (voltage detection 0 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Set the VW0C7 bit in the VW0C register to by the VW0F0 to VW0F1 bits in the VW0C 1 register Set the VW0C1 bit in the VW0C register to Set the VW0C1 bit in the VW0C register to 0 (digital filter enabled) 1 (digital filter disabled) Set the VW0C6 bit in the VW0C register to 1 (voltage monitor 0 reset mode) Set the VW0C2 bit in the VW0C register to 0 Set the CM14 bit in the CM1 register to 0 - (low-speed on-chip oscillator on) Wait for 4 cycles of the sampling clock of - (No wait time required) the digital filter Set the VW0C0 bit in the VW0C register to 1 (voltage monitor 0 reset enabled)
NOTE: 1. When the VW0C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction).
VCC Vdet0
Sampling clock of digital filter x 4 cycles When the VW0C1 bit is set to 0 (digital filter enabled) Internal reset signal
1 x 32 fOCO-S
1 x 32 fOCO-S
When the VW0C1 bit is set to 1 (digital filter disabled) and the VW0C7 bit is set to 1
Internal reset signal
VW0C1 and VW0C7: Bits in VW0C register The above applies under the following conditions. * VCA25 bit in VCA2 register = 1 (voltage detection 0 circuit enabled) * VW0C0 bit in VW0C register = 1 (voltage monitor 0 reset enabled) * VW0C6 bit in VW0C register = 1 (voltage monitor 0 reset mode) When the internal reset signal is held "L", the pins, CPU and SFR are reset. The internal reset signal level changes from "L" to "H", and a program is executed beginning with the address indicated by the reset vector. Refer to 4. Special Function Registers (SFRs) for the SFR status after reset.
Figure 6.9
Example of Voltage Monitor 0 Reset Operation
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 41 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
6.3
Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset
Table 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.10 shows an Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation. To use the voltage monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1 (digital filter disabled). Table 6.3 Step 1 2 3 4(2) 5(2) Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset When Using Digital Filter When Not Using Digital Filter Voltage Monitor 1 Voltage Monitor 1 Voltage Monitor 1 Voltage Monitor 1 Interrupt Reset Interrupt Reset Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Select the timing of the interrupt and reset request by the VW1C7 bit in the VW1C by the VW1F0 to VW1F1 bits in the VW1C register register(1) Set the VW1C1 bit in the VW1C register to 0 Set the VW1C1 bit in the VW1C register to 1 (digital filter enabled) (digital filter disabled) Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in Set the VW1C6 bit in the VW1C register to the VW1C register to the VW1C register to the VW1C register to 0 (voltage monitor 1 1 (voltage monitor 1 0 (voltage monitor 1 1 (voltage monitor 1 reset mode) interrupt mode) reset mode) interrupt mode) Set the VW1C2 bit in the VW1C register to 0 (passing of Vdet1 is not detected) Set the CM14 bit in the CM1 register to 0 - (low-speed on-chip oscillator on) Wait for 4 cycles of the sampling clock of the - (No wait time required) digital filter Set the VW1C0 bit in the VW1C register to 1 (voltage monitor 1 interrupt/reset enabled)
6 7 8 9
NOTES: 1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset. 2. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 42 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
VCC Vdet1
2.2 V(1)
1 VW1C3 bit 0 4 cycles of sampling clock of digital filter 1 VW1C2 bit 0 Set to 0 by a program When the VW1C1 bit is set to 0 (digital filter enabled) Set to 0 by interrupt request acknowledgement 4 cycles of sampling clock of digital filter
Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1)
Set to 0 by a program 1 When the VW1C1 bit is set to 1 (digital filter disabled) and the VW1C7 bit is set to 0 (Vdet1 or above) VW1C2 bit 0 Voltage monitor 1 interrupt request (VW1C6 = 0) Set to 0 by interrupt request acknowledgement
Set to 0 by a program 1 VW1C2 bit 0 When the VW1C1 bit is set to 1 (digital filter disabled) and the VW1C7 bit is set to 1 (Vdet1 or below) Voltage monitor 1 interrupt request (VW1C6 = 0) Internal reset signal (VW1C6 = 1) Set to 0 by interrupt request acknowledgement
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bit in VW1C Register
The above applies under the following conditions. * VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled) * VW1C0 bit in VW1C register = 1 (voltage monitor 1 interrupt and voltage monitor 1 reset enabled) NOTE: 1. If voltage monitor 0 reset is not used, set the power supply to VCC 2.2.
Figure 6.10
Example of Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 43 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
6.4
Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Table 6.4 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.11 shows an Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation. To use the voltage monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1 (digital filter disabled). Table 6.4 Step 1 2 3 4 5(2) Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset When Using Digital Filter When Not Using Digital Filter Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2 Voltage Monitor 2 Interrupt Reset Interrupt Reset Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled) Wait for td(E-A) Select the sampling clock of the digital filter Select the timing of the interrupt and reset request by the VW2C7 bit in the VW2C by the VW2F0 to VW2F1 bits in the VW2C register register(1) Set the VW2C1 bit in the VW2C register to 0 Set the VW2C1 bit in the VW2C register to 1 (digital filter enabled) (digital filter disabled) Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in Set the VW2C6 bit in the VW2C register to the VW2C register to the VW2C register to the VW2C register to 0 (voltage monitor 2 1 (voltage monitor 2 0 (voltage monitor 2 1 (voltage monitor 2 reset mode) interrupt mode) reset mode) interrupt mode) Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected) Set the CM14 bit in the CM1 register to 0 - (low-speed on-chip oscillator on) Wait for 4 cycles of the sampling clock of the - (No wait time required) digital filter Set the VW2C0 bit in the VW2C register to 1 (voltage monitor 2 interrupt/reset enabled)
6 7 8 9
NOTES: 1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset. 2. When the VW2C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1 instruction).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 44 of 485
R8C/24 Group, R8C/25 Group
6. Voltage Detection Circuit
VCC Vdet2
2.2 V(1)
1 VCA13 bit 0 4 cycles of sampling clock of digital filter 1 VW2C2 bit 0 Set to 0 by a program When the VW2C1 bit is set to 0 (digital filter enabled) Set to 0 by interrupt request acknowledgement 4 cycles of sampling clock of digital filter
Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1)
Set to 0 by a program 1 When the VW2C1 bit is set to 1 (digital filter disabled) and the VW2C7 bit is set to 0 (Vdet2 or above) VW2C2 bit 0 Voltage monitor 2 interrupt request (VW2C6 = 0) Set to 0 by interrupt request acknowledgement
Set to 0 by a program 1 VW2C2 bit 0 When the VW2C1 bit is set to 1 (digital filter disabled) and the VW2C7 bit is set to 1 (Vdet2 or below) Voltage monitor 2 interrupt request (VW2C6 = 0) Internal reset signal (VW2C6 = 1) Set to 0 by interrupt request acknowledgement
VCA13: Bit in VCA1 register VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register The above applies under the following conditions. * VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled) * VW2C0 bit in VW2C register = 1 (voltage monitor 2 interrupt and voltage monitor 2 reset enabled) NOTE: 1. When voltage monitor 0 reset is not used, set the power supply to VCC 2.2.
Figure 6.11
Example of Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 45 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
7.
Programmable I/O Ports
There are 41 programmable Input/Output ports (I/O ports) P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, and P6. Also, P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used, and the P4_2 can be used as an input-only port if the A/D converter is not used. Table 7.1 lists an Overview of Programmable I/O Ports. Table 7.1 Overview of Programmable I/O Ports I/O I/O I/O I/O I/O I Type of Output CMOS3 State CMOS3 State CMOS3 State CMOS3 State (No output function) I/O Setting Set per bit Set per bit Set per bit Set per bit None Internal Pull-Up Resister Set every 4 bits(1) Set every 3 bits(1) Set every bit(1) Set every 2 bits(1) None
Ports P0 to P2, P6 P3_0, P3_1, P3_3 to P3_4, P3_5, P3_7 P4_3 P4_4, P4_5 P4_2(2) P4_6, P4_7(3)
NOTES: 1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers PUR0 and PUR1. 2. When the A/D converter is not used, this port can be used as the input-only port. 3. When the XIN clock oscillation circuit is not used, these ports can be used as the input-only ports.
7.1
Functions of Programmable I/O Ports
The PDi_j (j = 0 to 7) bit in the PDi (i = 0 to 4, 6) register controls I/O of the ports P0 to P2, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, and P6. The Pi register consists of a port latch to hold output data and a circuit to read pin states. Figures 7.1 to 7.7 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of Programmable I/O Ports. Also, Figure 7.9 shows the PDi (i = 0 to 4 and 6) Registers. Figure 7.10 shows the Pi (i = 0 to 4 and 6) Registers, Figure 7.11 shows Registers PUR0 and PUR1, Figure 7.12 shows the PMR Register, Figure 7.13 shows the P2DRR Register. Table 7.2 Functions of Programmable I/O Ports
Operation When Value of PDi_j Bit in PDi Register(1) Accessing When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode) Pi Register Reading Read pin input level Read the port latch Write to the port latch. The value written to Writing Write to the port latch the port latch is output from the pin. i = 0 to 4, 6 j = 0 to 7 NOTE: 1. Nothing is assigned to bits PD3_2, PD3_6, PD4_0 to PD4_2, PD4_6, and PD4_7.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 46 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
7.2
Effect on Peripheral Functions
Programmable I/O ports function as I/O ports for peripheral functions (Refer to Table 1.6 Pin Name Information by Pin Number). Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4, 6 j = 0 to 7). Refer to the description of each function for information on how to set peripheral functions. Table 7.3 Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0 to 4, 6 j = 0 to 7)
I/O of Peripheral Functions PDi_j Bit Settings for Shared Pin Functions Input Set this bit to 0 (input mode). Output This bit can be set to either 0 or 1 (output regardless of the port setting)
7.3
Pins Other than Programmable I/O Ports
Figure 7.8 shows the Configuration of I/O Pins.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 47 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
P0
Direction register
Pull-up selection
(Note 1) Data bus Port latch (Note 1)
Analog input
P1_0 to P1_3
Direction register
Pull-up selection
1 (Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
Input to individual peripheral function Analog input
P1_4
Direction register
Pull-up selection
1 (Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC.
Figure 7.1
Configuration of Programmable I/O Ports (1)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 48 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
P1_5 and P1_7
Direction register
Pull-up selection
"1" (Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
INT1 input
Digital filter
Input to individual peripheral function
P1_6
Direction register
Pull-up selection
"1" (Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
Input to individual peripheral function
P2
Pull-up selection Direction register "1"
Drive capacity select
(Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
Input to individual peripheral function
Drive capacity select NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC.
Figure 7.2
Configuration of Programmable I/O Ports (2) Page 49 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
P3_0 and P3_1
Direction register
Pull-up selection
1 (Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
P3_3, P3_4, P3_5, and P3_7
Direction register
Pull-up selection
1 (Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
Input to individual peripheral function
NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC.
Figure 7.3
Configuration of Programmable I/O Ports (3)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 50 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
P4_2/VREF
Data bus
(Note 1)
(Note 1)
P4_3/XCIN
Direction register
Pull-up selection
(Note 1) Data bus Port latch (Note 1)
Clocked inverter(2) (Note 3)
P4_4/XCOUT
Direction register
Pull-up selection
(Note 1) Data bus Port latch (Note 1)
NOTES: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. 2. When CM10 = 1 or CM04 = 0, the clocked inverter is cut off. 3. When CM04 = 0 the feedback resistor is disconnected.
Figure 7.4
Configuration of Programmable I/O Ports (4)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 51 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
P4_5
Direction register
Pull-up selection
(Note 1) Data bus Port latch (Note 1)
INT0 and Input to individual peripheral function
Digital filter
P4_6/XIN
Data bus
(Note 1)
(Note 1)
Clocked inverter(2)
(Note 3)
P4_7/XOUT
(Note 4)
Data bus
(Note 1)
(Note 1)
NOTES: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC. 2. When CM05 = 1, CM10 = 1, or CM13 = 0, the clocked inverter is cut off. 3. When CM10 = 1 or CM13 = 0, the feedback resistor is disconnected. 4. When CM05 = CM13 = 1 or CM10 = CM13 = 1, this pin is pulled up.
Figure 7.5
Configuration of Programmable I/O Ports (5)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 52 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
P6_0
Direction register
Pull-up selection
1 (Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
P6_1, P6_2, P6_3, and P6_4
Direction register
Pull-up selection
(Note 1) Data bus Port latch (Note 1)
P6_5
Direction register
Pull-up selection
1 (Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
Input to individual peripheral function NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC.
Figure 7.6
Configuration of Programmable I/O Ports (6)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 53 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
P6_6
Direction register
Pull-up selection
1 (Note 1)
Output from individual peripheral function
Data bus
Port latch (Note 1)
INT2 input
Digital filter
P6_7
Direction register
Pull-up selection
(Note 1) Data bus Port latch (Note 1)
INT3 input
Digital filter
Input to individual peripheral function
NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC.
Figure 7.7
Configuration of Programmable I/O Ports (7)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 54 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
MODE
MODE signal input (Note 1)
RESET
RESET signal input
(Note 1)
(Note 1)
NOTE: 1. symbolizes a parasitic diode. Ensure the input voltage to each port does not exceed VCC.
Figure 7.8
Configuration of I/O Pins
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 55 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Port Pi Direction Register (i = 0 to 4, 6)(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD0(3) PD1 PD2 PD3 PD4 PD6 Bit Symbol PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Address 00E2h 00E3h 00E6h 00E7h 00EAh 00EEh Bit Name Port Pi_0 direction bit Port Pi_1 direction bit Port Pi_2 direction bit Port Pi_3 direction bit Port Pi_4 direction bit Port Pi_5 direction bit Port Pi_6 direction bit Port Pi_7 direction bit
After Reset 00h 00h 00h 00h 00h 00h Function 0 : Input mode (functions as an input port) 1 : Output mode (functions as an output port)
RW RW RW RW RW RW RW RW RW
NOTES: 1. Bits PD3_2 and PD3_6 in the PD3 register are unavailable on this MCU. If it is necessary to set bits PD3_2 and PD3_6, set to 0 (input mode). When read, the content is 0. 2. Bits PD4_0 to PD4_2, PD4_6, and PD4_7 in the PD4 register are unavailable on this MCU. If it is necessary to set bits PD4_0 to PD4_2, PD4_6 and PD4_7 in the PD4 register, set to 0 (input mode). When read, the content is 0. 3. Write to the PD0 register w ith the next instruction after that used to set the PRC2 bit in the PRCR register to 1 (w rite enabled).
Figure 7.9
PDi (i = 0 to 4 and 6) Registers
Port Pi Register (i = 0 to 4, 6)(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P0 P1 P2 P3 P4 P6 Bit Symbol Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Address 00E0h 00E1h 00E4h 00E5h 00E8h 00ECh Bit Name Port Pi_0 bit Port Pi_1 bit Port Pi_2 bit Port Pi_3 bit Port Pi_4 bit Port Pi_5 bit Port Pi_6 bit Port Pi_7 bit
After Reset Undefined Undefined Undefined Undefined Undefined Undefined Function The pin level of any I/O port w hich is set to input mode can be read by reading the corresponding bit in this register. The pin level of any I/O port w hich is set to output mode can be controlled by w riting to the corresponding bit in this register. 0 : "L" level 1 : "H" level
RW RW RW RW RW RW RW RW RW
NOTES: 1. Bits P3_2 and P3_6 in the P3 register are unavailable on this MCU. If it is necessary to set bits P3_2 and P3_6, set to 0 ("L" level). When read, the content is 0. 2. Bits P4_0 and P4_1 in the P4 register are unavailable on this MCU. If it is necessary to set bits P4_0 and P4_1, set to 0 ("L" level). When read, the content is 0.
Figure 7.10
Pi (i = 0 to 4 and 6) Registers Page 56 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Pull-Up Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0 Bit Symbol PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07
Address 00FCh Bit Name P0_0 to P0_3 pull-up(1) P0_4 to P0_7 pull-up(1) P1_0 to P1_3 pull-up(1) P1_4 to P1_7 pull-up(1) P2_0 to P2_3 pull-up(1) P2_4 to P2_7 pull-up(1) P3_0, P3_1, and P3_3 pll-up(1) P3_4 to P3_5, and P3_7 pll-up
(1)
After Reset 00h Function 0 : Not pulled up 1 : Pulled up 0 : Not pulled up 1 : Pulled up 0 : Not pulled up 1 : Pulled up 0 : Not pulled up 1 : Pulled up 0 : Not pulled up 1 : Pulled up
RW RW RW RW RW RW RW RW RW
NOTE: 1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Pull-Up Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol PUR1 Bit Symbol PU10 PU11 -- (b3-b2) PU14 PU15 -- (b7-b6) P4_3 pull-up(1)
Address 00FDh Bit Name
After Reset XX00XX00b Function 0 : Not pulled up 1 : Pulled up 0 : Not pulled up 1 : Pulled up Set to 0.
RW RW RW RW RW RW --
P4_4 and P4_5 pull-up(1) Reserved bits
P6_0 to P6_3 pull-up(1) 0 : Not pulled up 1 : Pulled up P6_4 to P6_7 pull-up(1) Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NOTE: 1. When this bit is set to 1 (pulled up), the pin w hose direction bit is set to 0 (input mode) is pulled up.
Figure 7.11
Registers PUR0 and PUR1
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 57 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
00
0000
Symbol Address 00F8h PMR Bit Symbol Bit Name -- Reserved bits (b3-b0) U1PINSEL -- (b6-b5) IICSEL Port CLK1/TXD1/RXD1 sw itch bit Reserved bits SSU / I2C bus sw itch bit
After Reset 00h Function Set to 0. 0 : I/O ports P6_5, P6_6, P6_7 1 : CLK1, TXD1, RXD1 Set to 0. 0 : Selects SSU function 1 : Selects I2C bus function
RW -- RW -- RW
Figure 7.12
PMR Register
Port P2 Drive Capacity Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P2DRR Bit Symbol P2DRR0 P2DRR1 P2DRR2 P2DRR3 P2DRR4 P2DRR5 P2DRR6 P2DRR7
Address 00F4h Bit Name P2_0 drive capacity P2_1 drive capacity P2_2 drive capacity P2_3 drive capacity P2_4 drive capacity P2_5 drive capacity P2_6 drive capacity P2_7 drive capacity
After Reset 00h Function Set P2 output transistor drive capacity 0 : Low 1 : High(1)
RW RW RW RW RW RW RW RW RW
NOTE: 1. Both "H" and "L" output are set to high drive capacity.
Figure 7.13
P2DRR Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 58 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
7.4
Port settings
Tables 7.4 to 7.47 list the port settings. Table 7.4
Register Bit Setting Value
Port P0_0/AN7
PD0 PD0_0 0 1 0 CH2 X X 1 X X 1 ADCON0 CH1 CH0 X X 1 ADGSEL0 X X 0 Input port(1) Output port A/D converter input (AN7) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
Table 7.5
Register Bit Setting Value
Port P0_1/AN6
PD0 PD0_1 0 1 0 CH2 X X 1 X X 1 ADCON0 CH1 CH0 X X 0 ADGSEL0 X X 0 Input port(1) Output port A/D converter input (AN6) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
Table 7.6
Register Bit Setting Value
Port P0_2/AN5
PD0 PD0_2 0 1 0 CH2 X X 1 X X 0 ADCON0 CH1 CH0 X X 1 ADGSEL0 X X 0 Input port(1) Output port A/D converter input (AN5) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
Table 7.7
Register Bit Setting Value
Port P0_3/AN4
PD0 PD0_3 0 1 0 CH2 X X 1 X X 0 ADCON0 CH1 CH0 X X 0 ADGSEL0 X X 0 Input port(1) Output port A/D converter input (AN4) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
Table 7.8
Register Bit Setting Value
Port P0_4/AN3
PD0 PD0_4 0 1 0 CH2 X X 0 X X 1 ADCON0 CH1 CH0 X X 1 ADGSEL0 X X 0 Input port(1) Output port A/D converter input (AN3) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 59 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.9
Register Bit Setting Value
Port P0_5/AN2
PD0 PD0_5 0 1 0 CH2 X X 0 X X 1 ADCON0 CH1 CH0 X X 0 ADGSEL0 X X 0 Input port(1) Output port A/D converter input (AN2) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Table 7.10
Register Bit Setting Value
Port P0_6/AN1
PD0 PD0_6 0 1 0 CH2 X X 0 X X 0 ADCON0 CH1 CH0 X X 1 ADGSEL0 X X 0 Input port(1) Output port A/D converter input (AN1) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Table 7.11
Register Bit Setting Value
Port P0_7/AN0
PD0 PD0_7 0 1 0 CH2 X X 0 X X 0 ADCON0 CH1 CH0 X X 0 ADGSEL0 X X 0 Input port(1) Output port A/D converter input (AN0) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Table 7.12
Register Bit Setting Value
Port P1_0/KI0/AN8
PD1 PD1_0 0 1 0 0 KIEN KI0EN X X 1 X CH2 X X X 1 X X X 0 ADCON0 CH1 CH0 X X X 0 ADGSEL0 X X X 1 Input port(1) Output port KI0 input A/D converter input (AN8) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.13
Register Bit Setting Value
Port P1_1/KI1/AN9
PD1 PD1_1 0 1 0 0 KIEN KI1EN X X 1 X CH2 X X X 1 X X X 0 ADCON0 CH1 CH0 X X X 1 ADGSEL0 X X X 1 Input port(1) Output port KI1 input A/D converter input (AN9) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 60 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.14
Register Bit Setting Value
Port P1_2/KI2/AN10
PD1 PD1_2 0 1 0 0 KIEN KI2EN X X 1 X CH2 X X X 1 X X X 1 ADCON0 CH1 CH0 X X X 0 ADGSEL0 X X X 1 Input port(1) Output port KI2 input A/D converter input (AN10) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.15
Register Bit Setting Value
Port P1_3/KI3/AN11
PD1 PD1_3 0 1 0 0 KIEN KI3EN X X 1 X CH2 X X X 1 X X X 1 ADCON0 CH1 CH0 X X X 1 ADGSEL0 X X X 1 Input port(1) Output port KI3 input A/D converter input (AN11) Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
Table 7.16
Register Bit
Port P1_4/TXD0
PD1 PD1_4 0 1 SMD2 0 0 0 X 1 1 1 U0MR SMD1 0 0 0 0 0 1 SMD0 0 0 1 0 1 0 TXD0 output(2) Input port(1) Output port Function
Setting Value
X: 0 or 1 NOTES: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the NCH bit in the U0C0 register to 1.
Table 7.17
Register Bit
Port P1_5/RXD0/(TRAIO)/(INT1)
PD1 PD1_5 0 0 X X 0 1 X X 0 0 0 X X 0 1 1 1 TRAIOC TIOSEL TOPCR X 1 X X 1 X X X X 0 0 0 X X TMOD2 X X TRAMR TMOD1 X X Other than 001b X X Other than 001b Other than 001b 0 Other than 001b Other than 001b 0 1 1 X X 1 X RXD0 input TRAIO input TRAIO/INT1 input TRAIO pulse output X X X Output port TMOD0 X X X Input port(1) INTEN INT1EN Function
Setting Value
X: 0 or 1 NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 61 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.18
Register Bit
Port P1_6/CLK0
PD1 PD1_6 0 SMD2 X X 0 SMD1 Other than 001b X Other than 001b X 0 X 1 X U0MR SMD0 CKDIR X 1 X 1 0 Input port(1) Output port CLK0 (external clock) input CLK0 (internal clock) output Function
Setting Value
1 0 X
X: 0 or 1 NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
Table 7.19
Register Bit
Port P1_7/TRAIO/INT1
PD1 PD1_7 0 1 X X 1 TRAIOC TIOSEL TOPCR X 1 X X 1 X X X 0 0 X X TMOD2 X X TRAMR TMOD1 X X Other than 001b X X Other than 001b Other than 001b Other than 001b 0 1 X 1 X TRAIO input TRAIO/INT1 input TRAIO pulse output X X X Output port TMOD0 X X X Input port(1) INTEN INT1EN Function
Setting Value
1 0 0 X
X X 0 0 0
X: 0 or 1 NOTE: 1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
Table 7.20
Register Bit PD2 PD2_0 0 1 Setting Value 0 0 X X
Port P2_0/TRDIOA0/TRDCLK
TRDOER1 EA0 1 1 X X 0 0 CMD1 X X 0 X 0 0 TRDFCR CMD0 X X 0 X 0 0 STCLK PWM3 X X 0 1 0 0 X X 1 1 0 1 IOA2 X X 1 0 X 0 0 TRDIORA0 IOA1 X X X 0 X 0 1 IOA0 X X X 0 X 1 X Input port(1) Output port(2) Timer mode (input capture function) External clock input (TRDCLK) PWM3 mode waveform output(2) Timer mode waveform output (output compare function)(2)
Function
X: 0 or 1 NOTES: 1. Pulled up by setting the PU04 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P2DRR0 bit in the P2DRR register to 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 62 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.21
Register Bit PD2 PD2_1 0 1 0 Setting Value X X X X X
Port P2_1/TRDIOB0
TRDOER1 EB0 1 1 X 0 0 0 0 0 X X 0 1 1 0 0 0 0 TRDFCR CMD1 CMD0 PWM3 X X 0 0 1 1 0 0 0 X X 1 X X 0 1 1 TRDPMR PWMB0 X X 0 X X X 1 0 X X 1 X X X X 0 0 TRDIORA0 IOB2 IOB1 IOB0 X X X X X X X 0 1 X X X X X X X 1 X Input port(1) Output port(2) Timer mode (input capture function) Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM3 mode waveform output(2) PWM mode waveform output(2) Timer mode waveform output (output compare function)(2) Function
X: 0 or 1 NOTES: 1. Pulled up by setting the PU04 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P2DRR1 bit in the P2DRR register to 1.
Table 7.22
Register Bit PD2 PD2_2 0 1 0 Setting Value X X X X
Port P2_2/TRDIOC0
TRDOER1 EC0 1 1 X 0 0 0 0 CMD1 X X 0 1 1 0 0 0 TRDFCR CMD0 PWM3 X X 0 0 1 1 0 0 X X 1 X X 1 1 TRDPMR PWMC0 X X 0 X X 1 0 X X 1 X X X 0 0 TRDIORC0 IOC2 IOC1 IOC0 X X X X X X 0 1 X X X X X X 1 X Input port(1) Output port(2) Timer mode (input capture function) Complementary PWM mode waveform output(2) Reset synchronous PWM mode waveform output(2) PWM mode waveform output(2) Timer mode waveform output (output compare function)(2) Function
X: 0 or 1 NOTES: 1. Pulled up by setting the PU04 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P2DRR2 bit in the P2DRR register to 1.
Table 7.23
Register Bit PD2 PD2_3 0 1 0 Setting Value X X X X
Port P2_3/TRDIOD0
TRDOER1 ED0 1 1 X 0 0 0 0 CMD1 X X 0 1 1 0 0 0 TRDFCR CMD0 PWM3 X X 0 0 1 1 0 0 X X 1 X X 1 1 TRDPMR PWMD0 X X 0 X X 1 0 X X 1 X X X 0 0 TRDIORC0 IOD2 IOD1 IOD0 X X X X X X 0 1 X X X X X X 1 X Input port(1) Output port(2) Timer mode (input capture function) Complementary PWM mode waveform output(2) Reset synchronous PWM mode waveform output(2) PWM mode waveform output(2) Timer mode waveform output (output compare function)(2) Function
X: 0 or 1 NOTES: 1. Pulled up by setting the PU04 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P2DRR3 bit in the P2DRR register to 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 63 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.24
Register Bit PD2 PD2_4 0 1 0 Setting Value X X X
Port P2_4/TRDIOA1
TRDOER1 EA1 1 1 X 0 0 0 CMD1 X X 0 1 1 0 0 TRDFCR X X 0 0 1 1 0 X X 1 X X 1 X X 1 X X 0 0 TRDIORA1 IOA1 IOA0 X X X X X 0 1 X X X X X 1 X Input port(1) Output port(2) Timer mode (input capture function) Complementary PWM mode waveform output(2) Reset synchronous PWM mode waveform output(2) Timer mode waveform output (output compare function)(2) CMD0 PWM3 IOA2 Function
X: 0 or 1 NOTES: 1. Pulled up by setting the PU05 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P2DRR4 bit in the P2DRR register to 1.
Table 7.25
Register Bit PD2 PD2_5 0 1 0 Setting Value X X X X
Port P2_5/TRDIOB1
TRDOER1 EB1 1 1 X 0 0 0 0 CMD1 X X 0 1 1 0 0 0 TRDFCR CMD0 PWM3 X X 0 0 1 1 0 0 X X 1 X X 1 1 TRDPMR PWMB1 X X 0 X X 1 0 X X 1 X X X 0 0 TRDIORA1 IOB2 IOB1 IOB0 X X X X X X 0 1 X X X X X X 1 X Input port(1) Output port(2) Timer mode (input capture function) Complementary PWM mode waveform output(2) Reset synchronous PWM mode waveform output(2) PWM mode waveform output(2) Timer mode waveform output (output compare function)(2) Function
X: 0 or 1 NOTES: 1. Pulled up by setting the PU05 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P2DRR5 bit in the P2DRR register to 1.
Table 7.26
Register Bit PD2 PD2_6 0 1 0 Setting Value X X X X
Port P2_6/TRDIOC1
TRDOER1 EC1 1 1 X 0 0 0 0 CMD1 X X 0 1 1 0 0 0 TRDFCR CMD0 PWM3 X X 0 0 1 1 0 0 X X 1 X X 1 1 TRDPMR PWMC1 X X 0 X X 1 0 X X 1 X X X 0 0 TRDIORC1 IOC2 IOC1 IOC0 X X X X X X 0 1 X X X X X X 1 X Input port(1) Output port(2) Timer mode (input capture function) Complementary PWM mode waveform output(2) Reset synchronous PWM mode waveform output(2) PWM mode waveform output(2) Timer mode waveform output (output compare function)(2) Function
X: 0 or 1 NOTES: 1. Pulled up by setting the PU05 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P2DRR6 bit in the P2DRR register to 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 64 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.27
Register Bit PD2 PD2_7 0 1 0 Setting Value X X X X
Port P2_7/TRDIOD1
TRDOER1 ED1 1 1 X 0 0 0 0 CMD1 X X 0 1 1 0 0 0 TRDFCR CMD0 PWM3 X X 0 0 1 1 0 0 X X 1 X X 1 1 TRDPMR PWMD1 X X 0 X X 1 0 X X 1 X X X 0 0 TRDIORC1 IOD2 IOD1 IOD0 X X X X X X 0 1 X X X X X X 1 X Input port(1) Output port(2) Timer mode (input capture function) Complementary PWM mode waveform output(2) Reset synchronous PWM mode waveform output(2) PWM mode waveform output(2) Timer mode waveform output (output compare function)(2) Function
X: 0 or 1 NOTES: 1. Pulled up by setting the PU05 bit in the PUR0 register to 1. 2. Output drive capacity high by setting the P2DRR7 bit in the P2DRR register to 1.
Table 7.28
Register Bit Setting Value
Port P3_0/TRAO
PD3 PD3_0 0 1 X TRAIOC TOENA 0 0 1 Input port(1) Output port TRAO output Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
Table 7.29
Register Bit Setting Value
Port P3_1/TRBO
PD3 PD3_1 0 1 X X TMOD1 0 0 01b Other than 00b TRBMR TMOD0 0 0 TRBIOC TOCNT X X 1 0 Input port(1) Output port TRBO output Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
Table 7.30
Register Bit
Port P3_3/SSI
PD3 PD3_3 0 Clock Synchronous Serial I/O with Chip Select (Refer to Table 16.4 Association between Communication Modes and I/O Pins.) SSI output control 0 X 0 X 0 1 SSI input control 0 X 0 X 1 0 PMR IICSEL 0 1 0 1 0 0 Input port(1) Output port(2) SSI input SSI output(2) Function
Setting Value
1 X X
X: 0 or 1 NOTES: 1. Pulled up by setting the PU06 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the SOOS bit in the SSMR2 register to 1 when this pin functions as output.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 65 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.31
Register Bit
Port P3_4/SDA/SCS
PD3 PD3_4 0 0 1 0 0 0 0 0 1 1 X SSMR2 CSS1 CSS0 0 0 0 0 1 0 1 X PMR IICSEL 0 X 0 X 0 0 1 ICCR1 ICE X 0 X 0 X X 1 Input port(1) Output port(2) SCS input SCS output(2) SDA input/output Function
Setting Value
1 X X X
X: 0 or 1 NOTES: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
Table 7.32
Register Bit
Port P3_5/SCL/SSCK
PD3 PD3_5 0 0 1 1 X X X Clock Synchronous Serial I/O with Chip Select (Refer to Table 16.4 Association between Communication Modes and I/O Pins.) SSCK output control 0 0 0 0 0 1 1 SSCK input control 0 0 0 0 1 0 0 PMR IICSEL 0 X 0 X 0 0 1 ICCR1 ICE X 0 X 0 0 0 1 Input port(1) Output port(2) SSCK input SSCK output(2) SCL input/output Function
Setting Value
X: 0 or 1 NOTES: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1. 2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
Table 7.33
Register Bit
Port P3_7/SSO
PD3 PD3_7 0 0 1 Clock Synchronous Serial I/O with Chip Select (Refer to Table 16.4 Association between Communication Modes and I/O Pins.) SSO output control 0 X 0 X 0 1 1 SSO input control 0 X 0 X 1 0 0 SSMR2 SOOS X X 0 0 0 0 1 PMR IICSEL 0 1 0 1 0 0 0 Input port(1) Output port SSO input SSO output (CMOS output) SSO output (N-channel open-drain output) Function
Setting Value
1 X X X
X: 0 or 1 NOTE: 1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
Table 7.34
Register Bit Setting Value
Port P4_2/VREF
ADCON1 VCUT 0 1 Input port Input port/VREF input Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 66 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.35
Register Bit
Port P4_3/XCIN
PD4 PD4_3 0 1 X CM0 CM04 0 0 1 1 1 1 CM1 CM10 X X 0 0 1 0 CM12 X X 0 1 0 1 0 1 Circuit specifications Oscillation buffer OFF OFF ON ON OFF OFF ON ON Feedback resistor OFF OFF ON OFF ON OFF ON OFF Input port(1) Output port XCIN-XCOUT oscillation (on-chip feedback resistor enabled) XCIN-XCOUT oscillation (on-chip feedback resistor disabled) XCIN-XCOUT oscillation stop External XCIN input Function
Setting Value
X X X
X: 0 or 1 NOTE: 1. Pulled up by setting the PU10 bit in the PUR1 register to 1.
Table 7.36
Register Bit
Port P4_4/XCOUT
PD4 PD4_4 0 1 X CM0 CM04 0 0 1 1 1 1 CM1 CM10 X X 0 0 1 0 CM12 X X 0 1 0 1 0 1 Circuit specifications Oscillation buffer OFF OFF ON ON OFF OFF ON ON Feedback resistor OFF OFF ON OFF ON OFF ON OFF Input port(1) Output port XCIN-XCOUT oscillation (on-chip feedback resistor enabled) XCIN-XCOUT oscillation (on-chip feedback resistor disabled) XCIN-XCOUT oscillation stop External XCOUT output (inverted output of XCIN)(2) Function
Setting Value
X X X
X: 0 or 1 NOTES: 1. Pulled up by setting the PU11 bit in the PUR1 register to 1. 2. Since the XCIN-XCOUT oscillation buffer operates with internal step-down power, the XCOUT output level cannot be used as the CMOS level signal directly.
Table 7.37
Register Bit Setting Value
Port P4_5/INT0
PD4 PD4_5 0 1 0 INTEN INT0EN X X 1 Input port(1) Output port INT0 input Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 67 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.38
Register Bit
Port P4_6/XIN
CM1 CM13 0 CM10 X 0 0 1 1 CM0 CM05 X 0 1 0 1 Circuit specifications Oscillation buffer OFF ON OFF OFF OFF Feedback resistor OFF ON ON OFF OFF Input port XIN-XOUT oscillation External XIN input XIN-XOUT oscillation stop XIN-XOUT oscillation stop Function
Setting Value
1 1 1 1
X: 0 or 1
Table 7.39
Register Bit
Port P4_7/XOUT
CM1 CM13 0 CM10 X 0 0 1 1 CM0 CM05 X 0 1 0 1 Circuit specifications Oscillation buffer OFF ON OFF OFF OFF Feedback resistor OFF ON ON OFF OFF Input port XIN-XOUT oscillation XOUT is "H" pull-up XIN-XOUT oscillation stop XIN-XOUT oscillation stop Function
Setting Value
1 1 1 1
X: 0 or 1
Table 7.40
Register Bit Setting Value
Port P6_0/TREO
PD6 PD6_0 0 1 X TRECR1 TOENA 0 0 1 Input port(1) Output port TREO output Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
Table 7.41
Register Bit Setting Value
Port P6_1
PD6 PD6_1 0 1 Input port(1) Output port Function
NOTE: 1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
Table 7.42
Register Bit Setting Value
Port P6_2
PD6 PD6_2 0 1 Input port(1) Output port Function
NOTE: 1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
Table 7.43
Register Bit Setting Value
Port P6_3
PD6 PD6_3 0 1 Input port(1) Output port Function
NOTE: 1. Pulled up by setting the PU14 bit in the PUR1 register to 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 68 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
Table 7.44
Register Bit Setting Value
Port P6_4
PD6 PD6_4 0 1 Input port(1) Output port Function
NOTE: 1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Table 7.45
Register Bit
Port P6_5/CLK1
PD6 PD6_5 0 PMR U1PINSEL X 0 X X 1 0 X 0 X 1 1 X X X 0 X X SMD2 U1MR SMD1 X X Other than 001b X X X 0 X X X 1 SMD0 X X CKDIR X X 1 X 0 1 0 CLK1 (external clock) input CLK1 (internal clock) output Output port Input port(1) Other than 001b Function
Setting Value
X: 0 or 1 NOTE: 1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Table 7.46
Register Bit
Port P6_6/INT2/TXD1
PD6 PD6_6 0 1 0 PMR U1PINSEL X 0 X 0 X SMD2 0 X 0 X X 0 X 1 1 1 1 0 X 1 1 1 1 U1MR SMD1 0 X 0 X X 0 0 0 1 0 0 0 1 SMD0 0 X 0 X X 1 0 1 0 1 0 1 0 1 X TXD1 output (N-channel open-drain output) 0 X TXD1 output (CMOS output) U1C0 NCH X X X INTEN INT2EN X X 1 Input port(1) Output port INT2 input Function
Setting Value
X: 0 or 1 NOTE: 1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Table 7.47
Register Bit Setting Value
Port P6_7/INT3/RXD1
PD6 PD6_7 0 1 0 0 PMR U1PINSEL X X X 1 INTEN INT3EN X X 1 X Input port(1) Output port INT3 input RXD1 input Function
X: 0 or 1 NOTE: 1. Pulled up by setting the PU15 bit in the PUR1 register to 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 69 of 485
R8C/24 Group, R8C/25 Group
7. Programmable I/O Ports
7.5
Unassigned Pin Handling
Table 7.48 lists the Unassigned Pin Handling. Table 7.48 Unassigned Pin Handling Connection * After setting to input mode, connect each pin to VSS via a resistor (pulldown) or connect each pin to VCC via a resistor (pull-up).(2) * After setting to output mode, leave these pins open.(1,2) Connect to VCC via a pull-up resistor(2) Connect to VCC Connect to VCC via a pull-up resistor(2) Open or Connect to VCC and VSS
Pin Name Ports P0 to P2, P3_0, P3_1, P3_3 to P3_7, P4_3 to P4_5, P6 Ports P4_6, P4_7 Port P4_2, VREF RESET (3) NC
NOTES: 1. If these ports are set to output mode and left open, they remain in input mode until they are switched to output mode by a program. The voltage level of these pins may be undefined and the power current may increase while the ports remain in input mode. The content of the direction registers may change due to noise or program runaway caused by noise. In order to enhance program reliability, the program should periodically repeat the setting of the direction registers. 2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible. 3. When the power-on reset function is in use.
MCU
Port P0 to P2, P3_0, (Input mode ) : P3_1, P3_3 to P3_7, : P4_3 to P4_5, P6 (Input mode) (Output mode)
: : Open
Port P4_6, P4_7 RESET(1)
Port P4_2/VREF
NOTE: 1. When the power-on reset function is in use.
Figure 7.14
Unassigned Pin Handling
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 70 of 485
R8C/24 Group, R8C/25 Group
8. Processor Mode
8.
8.1
Processor Mode
Processor Modes
Single-chip mode can be selected as the processor mode. Table 8.1 lists Features of Processor Mode. Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register. Table 8.1 Features of Processor Mode Accessible Areas Pins Assignable as I/O Port Pins SFR, internal RAM, internal ROM All pins are I/O ports or peripheral function I/O pins
Processor Mode Single-chip mode
Processor Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol Address PM0 0004h Bit Symbol Bit Name Reserved bits -- (b2-b0) PM03 -- (b7-b4) Softw are reset bit
After Reset 00h Function Set to 0. The MCU is reset w hen this bit is set to 1. When read, the content is 0.
RW RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NOTE: 1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register.
Figure 8.1
PM0 Register
Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol Address PM1 0005h Bit Symbol Bit Name -- Reserved bits (b1-b0) PM12 -- (b6-b3) -- (b7) WDT interrupt/reset sw itch bit
After Reset 00h Function Set to 0. 0 : Watchdog timer interrupt 1 : Watchdog timer reset(2)
RW RW RW -- RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Reserved bit Set to 0.
NOTES: 1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register. 2. The PM12 bit is set to 1 by a program (and remains unchanged even if 0 is w ritten to it). When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is automatically set to 1.
Figure 8.2
PM1 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 71 of 485
R8C/24 Group, R8C/25 Group
9. Bus
9.
Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by Access Space of the R8C/24 Group and Table 9.2 lists Bus Cycles by Access Space of the R8C/25 Group. ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are accessed twice in 8-bit units. Table 9.3 lists Access Units and Bus Operations. Table 9.1 Bus Cycles by Access Space of the R8C/24 Group Bus Cycle 2 cycles of CPU clock 1 cycle of CPU clock
Access Area SFR ROM/RAM Table 9.2
Bus Cycles by Access Space of the R8C/25 Group Bus Cycle 2 cycles of CPU clock 1 cycle of CPU clock
Access Area SFR/Data flash Program ROM/RAM Table 9.3
Area Even address Byte access
Access Units and Bus Operations
SFR, data flash CPU clock Address Data Even Data ROM (program ROM), RAM CPU clock Address Data CPU clock Odd Data Address Data CPU clock Even Data Even+1 Data Address Data CPU clock Odd Data Odd+1 Data Address Data Odd Data Odd+1 Data Even Data Even+1 Data Odd Data Even Data
Odd address Byte access
CPU clock Address Data
Even address Word access
CPU clock Address Data
Odd address Word access
CPU clock Address Data
However, only following SFRs are connected with the 16-bit bus: Timer RD: registers TRDi (i = 0,1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi Therefore, they are accessed once in 16-bit units. The bus operation is the same as "Area: SFR, data flash, even address byte access" in Table 9.3 Access Units and Bus Operations, and 16-bit data is accessed at a time.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 72 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10. Clock Generation Circuit
The clock generation circuit has: * XIN clock oscillation circuit * XCIN clock oscillation circuit * Low-speed on-chip oscillator * High-speed on-chip oscillator Table 10.1 lists the Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figures 10.2 to 10.8 show clock associated registers. Figure 10.9 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. Table 10.1
Item Applications
Specifications of Clock Generation Circuit
XIN Clock Oscillation Circuit XCIN Clock Oscillation Circuit On-Chip Oscillator High-Speed On-Chip Low-Speed On-Chip Oscillator Oscillator * CPU clock source * CPU clock source * Peripheral function * Peripheral function clock source clock source * CPU and peripheral * CPU and peripheral function clock function clock sources when XIN sources when XIN clock stops oscillating clock stops oscillating Approx. 125 kHz Approx. 40 MHz(4) - -(1) Usable Stop - - -(1) Usable Oscillate -
* CPU clock source * CPU clock source * Peripheral function * Timer RA and timer RE clock source clock source
Clock frequency Connectable oscillator Oscillator connect pins Oscillation stop, restart function Oscillator status after reset Others
0 to 20 MHz
32.768 kHz
* Ceramic resonator * Crystal oscillator * Crystal oscillator XIN, XOUT(1) Usable Stop XCIN, XCOUT(2) Usable Stop
* Externally generated Externally generated clock can clock can be input * On-chip feedback be input(3) resistor Rf (connected/ not connected, selectable)
NOTES: 1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the XIN clock oscillation circuit is not used. 2. These pins can be used as P4_3 and P4_4 when using the XIN clock oscillation circuit and on-chip oscillator clock for a CPU clock while the XCIN clock oscillation circuit is not used. 3. Set the CM05 bit in the CM0 register to 1 (XIN clock stopped) and the CM13 bit in the CM1 register to 1 (XINXOUT pin) when an external clock is input. 4. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip oscillator as the CPU clock source.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 73 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
Clock prescaler fC4 fC FRA1 register Frequency adjustable FRA00 XCIN XCOUT High-speed on-chip oscillator fOCO40M FRA2 register Divider fOCO-F FRA01 = 1 FRA01 = 0 CM04 CM14 Low-speed on-chip oscillator fOCO On-chip oscillator clock Power-on reset circuit Voltage detection circuit b RESET Power-on reset Software reset Interrupt request WAIT instruction f1 c Oscillation stop detection XIN clock OCD2 = 1 g f32 h fC CM07 = 1 CM07 = 0 CPU clock d e f2 f4 f8 INT0 Divider (1/128) fOCO128 Watchdog timer A/D Timer RB Timer RD Timer RE converter SSU / I2C bus 1/4 1/8 fC32
Timer RA
UART0
UART1
fOCO-S
CM10 = 1 (stop mode)
SQ R
SQ R
CM13
a OCD2 = 0
Divider
XIN
XOUT
CM13 CM05 System clock CM02
b a 1/2
c 1/2
d 1/2
e 1/2 1/2
g
CM06 = 0 CM17 to CM16 = 11b CM06 = 1 CM06 = 0 CM17 to CM16 = 10b CM02, CM04, CM05, CM06, CM07: Bits in CM0 register CM10, CM13, CM14, CM16, CM17: Bits in CM1 register OCD0, OCD1, OCD2: Bits in OCD register FRA00, FRA01: Bits in FRA0 register CM06 = 0 CM17 to CM16 = 01b CM06 = 0 CM17 to CM16 = 00b
h
Detail of divider Oscillation Stop Detection Circuit
Forcible discharge when OCD0 = 0
XIN clock
Pulse generation circuit for clock edge detection and charge, discharge control circuit
Charge, discharge circuit OCD1
Oscillation stop detection interrupt generation circuit detection Watchdog timer interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt OCD2 bit switch signal CM14 bit switch signal
Oscillation stop detection, Watchdog timer, Voltage monitor 1 interrupt, Voltage monitor 2 interrupt
Figure 10.1
Clock Generation Circuit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 74 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol Address 0006h CM0 Bit Symbol Bit Name -- Reserved bits (b1-b0) WAIT peripheral function clock stop bit
After Reset 01101000b Function Set to 0. 0 : Peripheral function clock does not stop in w ait mode 1 : Peripheral function clock stops in w ait mode 0 : Low 1 : High
(6)
RW RW
CM02
RW
CM03 CM04 CM05 CM06 CM07
XCIN-XCOUT drive capacity select bit(9) Port, XCIN-XCOUT sw itch bit XIN clock (XIN-XOUT) stop bit(2, 4) System clock division select bit 0(5) CPU clock select bit
(8)
RW RW RW RW RW
0 : I/O port P4_3, P4_4 1 : XCIN-XCOUT pin(7) 0 : XIN clock oscillates 1 : XIN clock stops (3) 0 : CM16, CM17 enabled 1 : Divide-by-8 mode 0 : System clock 1 : XCIN clock
NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM0 register. 2. The CM05 bit stops the XIN clock w hen the high-speed on-chip oscillator mode, low -speed on-chip oscillator mode is selected. Do not use this bit to detect w hether the XIN clock is stopped. To stop the XIN clock, set the bits in the follow ing order: (a) Set bits OCD1 to OCD0 in the OCD register to 00b. (b) Set the OCD2 bit to 1 (selects on-chip oscillator clock). 3. During external clock input, only the clock oscillation buffer is turned off and clock input is acknow ledged. 4. When the CM05 bit is set to 1 (XIN clock stopped) and the CM13 bit in the CM1 register is set to 0 (P4_6, P4_7), P4_6 and P4_7 can be used as input ports. 5. When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode). 6. The CM04 bit can be set to 1 by a program but cannot be set to 0. 7. To use the XCIN clock, set the CM04 bit to 1. Also, set ports P4_3 and P4_4 as input ports w ithout pull-up. 8. Set the CM07 bit to 1 from 0 (XCIN clock) after setting the CM04 bit to 1 (XCIN-XCOUT pin) and allow ing XCIN clock oscillation to stabilize. 9. The MCU enters stop mode, the CM03 bit is set to 1 (high). Rew rite the CM03 bit w hile the XCIN clock oscillation stabilizes.
Figure 10.2
CM0 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 75 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
System Clock Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM1 Bit Symbol CM10 CM11 CM12 CM13 CM14 CM15
Address 0007h Bit Name All clock stop control bit(4, 7, 8)
After Reset 00100000b Function 0 : Clock operates 1 : Stops all clocks (stop mode)
RW RW RW RW RW RW RW
XIN-XOUT on-chip feedback resistor 0 : On-chip feedback resistor enabled select bit 1 : On-chip feedback resistor disabled XCIN-XCOUT on-chip feedback resistor select bit Port XIN-XOUT sw itch bit
(7, 9)
0 : On-chip feedback resistor enabled 1 : On-chip feedback resistor disabled 0 : Input ports P4_6, P4_7 1 : XIN-XOUT pin 0 : Low -speed on-chip oscillator on 1 : Low -speed on-chip oscillator off 0 : Low 1 : High
b7 b6
Low -speed on-chip oscillation stop bit(5, 6, 8) XIN-XOUT drive capacity select bit System clock division select bits 1
(2)
(3)
CM16
CM17
0 0 : No division mode 0 1 : Divide-by-2 mode 1 0 : Divide-by-4 mode 1 1 : Divide-by-16 mode
RW
RW
NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the CM1 register. 2. When entering stop mode, the CM15 bit is set to 1 (drive capacity high). 3. When the CM06 bit is set to 0 (bits CM16, CM17 enabled), bits CM16 to CM17 are enabled. 4. If the CM10 bit is set to 1 (stop mode), the on-chip feedback resistor is disabled. 5. When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit is set to 1 (low -speed on-chip oscillator stopped). When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip oscillator on). It remains unchanged even if 1 is w ritten to it. 6. When using the voltage monitor 1 interrupt or voltage monitor 2 interrupt (w hen using the digital filter), set the CM14 bit to 0 (low -speed on-chip oscillator on). 7. When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin goes "H". When the CM13 bit is set to 0 (input ports, P4_6, P4_7), P4_7 (XOUT) enters input mode. 8. In count source protect mode (Refer to 13.2 Count Source Protection Mode Enabled), the value remains unchanged even if bits CM10 and CM14 are set. 9. Once the CM13 bit is set to 1 by a program, it cannot be set to 0.
Figure 10.3
CM1 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 76 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
Oscillation Stop Detection Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol OCD Bit Symbol
OCD0
Address After Reset 000Ch 00000100b Bit Name Function Oscillation stop detection enable 0 : Oscillation stop detection function disabled(2) bit(7) 1 : Oscillation stop detection function enabled Oscillation stop detection interrupt enable bit System clock select bit Clock monitor bit(5, 6) Reserved bits
(4)
RW
RW
OCD1 OCD2 OCD3 -- (b7-b4)
0 : Disabled(2) 1 : Enabled 0 : Selects XIN clock 1 : Selects on-chip oscillator clock(3) 0 : XIN clock oscillates 1 : XIN clock stops Set to 0.
(7)
RW RW RO RW
NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting to the OCD register. 2. Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip oscillator mode (XIN clock stops). 3. The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock selected). 4. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected w hile bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stopped), the OCD2 bit remains unchanged even w hen set to 0 (XIN clock selected). 5. The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled). 6. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b. 7. Refer to Figure 10.16 Procedure for Sw itching Clock Source from Low -Speed On-Chip Oscillator to XIN Clock for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.
Figure 10.4
OCD Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 77 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol FRA0 Bit Symbol FRA00 FRA01 -- (b7-b2)
Address 0023h Bit Name High-speed on-chip oscillator enable bit High-speed on-chip oscillator select bit(2) Reserved bits
After Reset 00h Function 0 : High-speed on-chip oscillator off 1 : High-speed on-chip oscillator on 0 : Selects low -speed on-chip oscillator 1 : Selects high-speed on-chip oscillator Set to 0.
(3)
RW RW RW RW
NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA0 register. 2. Change the FRA01 bit under the follow ing conditions. * FRA00 = 1 (high-speed on-chip oscillation) * The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on) * Bits FRA22 to FRA20 in the FRA2 register: All divide ratio mode settings are supported w hen VCC = 3.0 V to 5.5 V 000b to 111b Divide ratio of 4 or more w hen VCC = 2.7 V to 5.5 V 010b to 111b (divide by 4 or more) Divide ratio of 8 or more w hen VCC = 2.2 V to 5.5 V 110b to 111b (divide by 8 or more) 3. When setting the FRA01 bit to 0 (low -speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high-speed on-chip oscillator off) at the same time. Set the FRA00 bit to 0 after setting the FRA01 bit to 0.
High-Speed On-Chip Oscillator Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol FRA1
Address 0024h
After Reset When Shipping RW
Function The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7. High-speed on-chip oscillator frequency = 40 MHz (FRA1 register = value w hen shipping) Setting the FRA1 register to a low er value results in a higher frequency. Setting the FRA1 register to a higher value results in a low er frequency.(2)
RW
NOTES: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA1 register. 2. When changing the values of the FRA1 register, adjust the FRA1 register so that the frequency of the high-speed on-chip oscillator clock w ill be 40 MHz or less.
Figure 10.5
Registers FRA0 and FRA1
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 78 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
High-Speed On-Chip Oscillator Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol FRA2 Bit Symbol
FRA20
Address 0025h Bit Name High-speed on-chip oscillator frequency sw itching bits
After Reset 00h Function Selects the dividing ratio for the highspeed on-chip oscillator clock.
b2 b1 b0
RW
RW
FRA21
FRA22
0 0 0: Divide-by-2 mode 0 0 1: Divide-by-3 mode 0 1 0: Divide-by-4 mode 0 1 1: Divide-by-5 mode 1 0 0: Divide-by-6 mode 1 0 1: Divide-by-7 mode 1 1 0: Divide-by-8 mode 1 1 1: Divide-by-9 mode
RW
RW
-- (b7-b3)
Reserved bits
Set to 0.
RW
NOTE: 1. Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rew riting the FRA2 register.
High-Speed On-Chip Oscillator Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol FRA4
Address 0029h
After Reset When Shipping RW RO
Function Stores data for frequency correction w hen VCC = 2.7 to 5.5 V. (The value is the same as that of the FRA1 register after a reset.) Optimal frequency correction to match the voltage conditions can be achieved by transferring this value to the FRA1 register.
High-Speed On-Chip Oscillator Control Register 6
b7 b6 b5 b4 b3 b2 b1 b0
Symbol FRA6
Address 002Bh
After Reset When Shipping RW RO
Function Stores data for frequency correction w hen VCC = 2.2 to 5.5 V. Optimal frequency correction to match the voltage conditions can be achieved by transferring this value to the FRA1 register.
High-Speed On-Chip Oscillator Control Register 7
b7 b6 b5 b4 b3 b2 b1 b0
Symbol FRA7
Address 002Ch
After Reset When Shipping RW RO
Function 36.864 MHz frequency correction data is stored. The oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 MHz by transferring this value to the FRA1 register.
Figure 10.6
Registers FRA2, FRA4, FRA6 and FRA7 Page 79 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
Clock Prescaler Reset Flag
b7 b6 b5 b4 b3 b2 b1 b0
0000000
Symbol Address 0028h CPSRF Bit Symbol Bit Name -- Reserved bits (b6-b0) CPSR Clock prescaler reset flag
(1)
After Reset 00h Function Set to 0. Setting this bit to 1 initializes the clock prescaler. (When read, the content is 0)
RW RW RW
NOTE: 1. Only w rite 1 to this bit w hen selecting the XCIN clock as the CPU clock, .
Figure 10.7
CPSRF Register
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol
Address
VCA2 Bit Symbol VCA20 -- (b4-b1) VCA25 VCA26 VCA27
0032h Bit Name Internal pow er low consumption enable bit(6) Reserved bits Voltage detection 0 enable bit(2) Voltage detection 1 enable bit(3) Voltage detection 2 enable bit(4)
After Reset(5) The LVD0ON bit in the OFS register is set to 1 and hardw are reset : 00h Pow er-on reset, voltage monitor 0 reset or LVD0ON bit in the OFS register is set to 0, and hardw are reset : 00100000b Function 0 : Disables low consumption 1 : Enables low consumption Set to 0. 0 : Voltage detection 0 circuit disabled 1 : Voltage detection 0 circuit enabled 0 : Voltage detection 1 circuit disabled 1 : Voltage detection 1 circuit enabled 0 : Voltage detection 2 circuit disabled 1 : Voltage detection 2 circuit enabled RW RW RW RW RW RW
NOTES: 1. Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register. 2. To use the voltage monitor 0 reset, set the VCA25 bit to 1. After the VCA25 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 3. To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1. After the VCA26 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 4. To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1. After the VCA27 bit is set to 1 from 0, the voltage detection circuit w aits for td(E-A) to elapse before starting operation. 5. Softw are reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this register. 6. Use the VCA20 bit only w hen entering to w ait mode. To set the VCA20 bit, follow the procedure show n in Figure 10.9 Procedure for Enabling Reduced Internal Pow er Consum ption Using VCA20 bit.
Figure 10.8
VCA2 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 80 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
Exit wait mode by interrupt Handling procedure of internal power low consumption enabled by VCA20 bit
(Note 1)
In interrupt routine
Step (1)
Enter low-speed clock mode or low-speed on-chip oscillator mode
Step (5)
VCA20 0 (internal power low consumption disabled)(2)
Step (2)
Stop XIN clock and high-speed on-chip oscillator clock
Step (6)
Start XIN clock or high-speed on-chip oscillator clock
Step (3)
VCA20 1 (internal power low consumption enabled)(2, 3)
Step (7)
(Wait until XIN clock oscillation stabilizes)
If it is necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (7) in the interrupt routine.
Step (4)
Enter wait mode(4)
Step (8)
Enter high-speed clock mode or high-speed on-chip oscillator mode
Step (5)
VCA20 0 (internal power low consumption disabled)(2)
Interrupt handling
Step (6)
Start XIN clock or high-speed on-chip oscillator clock
Step (1)
Enter low-speed clock mode or low-speed on-chip oscillator mode If the high-speed clock or high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine.
Step (2) Step (7) (Wait until XIN clock oscillation stabilizes)
Stop XIN clock and high-speed on-chip oscillator clock
Step (8)
Enter high-speed clock mode or high-speed on-chip oscillator mode
Step (3)
VCA20 1 (internal power low consumption enabled)(2, 3)
Interrupt handling completed NOTES: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite. 3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode). 4. When entering wait mode, follow 10.7.2 Wait Mode. VCA20: Bit in VCA2 register
Figure 10.9
Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 81 of 485
R8C/24 Group, R8C/25 Group The clocks generated by the clock generation circuits are described below.
10. Clock Generation Circuit
10.1
XIN Clock
This clock is supplied by the XIN clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between the XIN and XOUT pins. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 10.10 shows Examples of XIN Clock Connection Circuit. In reset and after reset, the XIN clock stops. The XIN clock starts oscillating when the CM05 bit in the CM0 register is set to 0 (XIN clock oscillates) after setting the CM13 bit in the CM1 register to 1 (XIN- XOUT pin). To use the XIN clock for the CPU clock source, set the OCD2 bit in the OCD register to 0 (select XIN clock) after the XIN clock is oscillating stably. The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 (XIN clock stops) if the OCD2 bit is set to 1 (select on-chip oscillator clock). When an external clock is input to the XIN pin are input, the XIN clock does not stop if the CM05 bit is set to 1. If necessary, use an external circuit to stop the clock. In stop mode, all clocks including the XIN clock stop. Refer to 10.5 Power Control for details.
MCU (on-chip feedback resistor) XIN Rf(1) XOUT Rd(1)
MCU (on-chip feedback resistor) XIN XOUT Open Externally derived clock
CIN
COUT
VCC VSS
Ceramic resonator external circuit
External clock input circuit
NOTE: 1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator. Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so after oscillation stabilizes. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN and XOUT following the instructions. To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally.
Figure 10.10
Examples of XIN Clock Connection Circuit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 82 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.2
On-Chip Oscillator Clocks
These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.
10.2.1
Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock, peripheral function clock, fOCO, and fOCO-S. After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as the CPU clock. If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU. The frequency of the low-speed on-chip oscillator varies depending on the supply voltage and the operating ambient temperature. Application products must be designed with sufficient margin to allow for frequency changes.
10.2.2
High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock, peripheral function clock, fOCO, fOCO-F, and fOCO40M. To use the high-speed on-chip oscillator clock as the clock source for the CPU clock, peripheral clock, fOCO, and fOCO-F, set bits FRA20 to FRA22 in the FRA2 register as follows: * All divide ratio mode settings are supported when VCC = 3.0 V to 5.5 V 000b to 111b * Divide ratio of 4 or more when VCC = 2.7 V to 5.5 V 010b to 111b (divide by 4 or more) * Divide ratio of 8 or more when VCC = 2.2 V to 5.5 V 110b to 111b (divide by 8 or more) After reset, the on-chip oscillator clock generated by the high-speed on-chip oscillator stops. Oscillation is started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can be adjusted by registers FRA1 and FRA2. The frequency correction data (the value is the same as that of the FRA1 register after a reset) corresponding to the supply voltage ranges VCC = 2.7 V to 5.5 V is stored in FRA4 register. Furthermore, the frequency correction data corresponding to the supply voltage ranges VCC = 2.2 V to 5.5 V is stored in FRA6 register. To use separate correction values to match these voltage ranges, transfer them from FRA4 or FRA6 register to the FRA1 register. The frequency correction data of 36.864 MHz is stored in the FRA7 register. To set the frequency of the highspeed on-chip oscillator to 36.864 MHz, transfer the correction value in the FRA7 register to the FRA1 register before use. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode (refer to Table 15.7 Bit Rate Setting Example in UART Mode (Internal Clock Selected)). Since there are differences in the amount of frequency adjustment among the bits in the FRA1 register, make adjustments by changing the settings of individual bits. Adjust the FRA1 register so that the frequency of the high-speed on-chip oscillator clock will be 40 MHz or less.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 83 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.3
XCIN Clock
This clock is supplied by the XCIN clock oscillation circuit. This clock is used as the clock source for the CPU clock, timer RA, and timer RE. The XCIN clock oscillation circuit is configured by connecting a resonator between the XCIN and XCOUT pins. The XCIN clock oscillation circuit includes an on-chip a feedback resistor, which is disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed in the chip. The XCIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 10.11 shows Examples of XCIN Clock Connection Circuits. During and after reset, the XCIN clock stops. The XCIN clock starts oscillating when the CM04 bit in the CM0 register is set to 1 (XCIN-XCOUT pin). To use the XCIN clock for the CPU clock source, set the CM07 bit in the CM0 register to 1 (XCIN clock) after the XCIN clock is oscillating stably. To input an external clock to the XCIN pin, set the CM04 bit in the CM0 register to 1 (XCIN-XCOUT pin) and leave the XCOUT pin open. This MCU has an on-chip feedback resistor and on-chip resistor disable/enable switching is possible by the CM12 bit in the CM1 register. In stop mode, all clocks including the XCIN clock stop. Refer to 10.5 Power Control for details.
MCU (on-chip feedback resistor) XCIN Rf(1) XCOUT
MCU (on-chip feedback resistor) XCIN XCOUT Open Rd(1) Externally derived clock
CIN
COUT
VCC VSS
External crystal oscillator circuit
External clock input circuit
NOTE: 1. Insert a damping resistor and feedback resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the manufacturer of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added to the chip externally, insert a feedback resistor between XCIN and XCOUT following the instructions.
Figure 10.11
Examples of XCIN Clock Connection Circuits
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 84 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.4
CPU Clock and Peripheral Function Clock
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer to Figure 10.1 Clock Generation Circuit.
10.4.1
System Clock
The system clock is the clock source for the CPU and peripheral function clocks. Either the XIN clock or the on-chip oscillator clock can be selected.
10.4.2
CPU Clock
The CPU clock is an operating clock for the CPU and watchdog timer. When the CM07 bit in the CM0 register is set to 0 (system clock), the system clock can be divided by 1 (no division), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register to select the value of the division. When the CM07 bit in the CM0 register is set to 1 (XCIN clock), the XCIN clock is used for the CPU clock. Use the XCIN clock while the XCIN clock oscillation stabilizes. After reset, the low-speed on-chip oscillator clock divided by 8 provides the CPU clock. When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode).
10.4.3
Peripheral Function Clock (f1, f2, f4, f8, and f32)
The peripheral function clock is the operating clock for the peripheral functions. The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for timers RA, RB, RD, and RE, the serial interface and the A/D converter. When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to 1 (peripheral function clock stops in wait mode), the clock fi stop.
10.4.4
fOCO
fOCO is an operating clock for the peripheral functions. fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA. When the WAIT instruction is executed, the clocks fOCO does not stop.
10.4.5
fOCO40M
fOCO40M is used as the count source for timer RD. fOCO40M is generated by the high-speed on-chip oscillator and supplied by setting the FRA00 bit to 1. When the WAIT instruction is executed, the clock fOCO40M does not stop. fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V.
10.4.6
fOCO-F
fOCO-F is used as the count source for the A/D converter. fOCO-F is generated by the high-speed on-chip oscillator and supplied by setting the FRA00 bit to 1. When the WAIT instruction is executed, the clock fOCO-F does not stop.
10.4.7
fOCO-S
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed onchip oscillator. When the WAIT instruction is executed or in count source protect mode of the watchdog timer, fOCO-S does not stop.
10.4.8
fOCO128
fOCO128 is generated by fOCO divided by 128. The clock fOCO128 is used for capture signal of timer RD (channel 0).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 85 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.4.9
fC4 and fC32
The clock fC4 and fC32 are used for timer RA and timer RE. Use fC4 and fC32 while the XCIN clock oscillation stabilizes.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 86 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.5
Power Control
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard operating mode.
10.5.1
Standard Operating Mode
Standard operating mode is further separated into four modes. In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power consumption is further reduced. Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating and stable. If the new clock source is the XIN clock or XCIN clock, allow sufficient wait time in a program until oscillation is stabilized before exiting. Table 10.2 Settings and Modes of Clock Associated Bits
OCD Register OCD2 High-speed clock mode No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 No division No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 No division Divide-by-2 Divide-by-4 Divide-by-8 Divide-by-16 0 0 0 0 0 - 1 1 1 1 1 1 1 1 1 1 CM1 Register CM17, CM16 00b 01b 10b - 11b - 00b 01b 10b - 11b 00b 01b 10b - 11b CM14 - - - - - - - - - - - 0 0 0 0 0 CM13 1 1 1 1 1 - - - - - - - - - - - CM07 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 CM0 Register CM06 0 0 0 1 0 - 0 0 0 1 0 0 0 0 1 0 CM05 0 0 0 0 0 - - - - - - - - - - - FRA0 Register CM04 FRA01 FRA00 - - - - - 1 - - - - - - - - - - - - - - - - 1 1 1 1 1 0 0 0 0 0 - - - - - - 1 1 1 1 1 - - - - -
Modes
Low-speed clock mode High-speed on-chip oscillator mode
Low-speed on-chip oscillator mode
X: can be 0 or 1, no change in outcome
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 87 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.5.1.1
High-Speed Clock Mode
The XIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divideby-8 mode) when transiting to high-speed on-chip oscillator mode, low-speed on-chip oscillator mode. If the CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (highspeed on-chip oscillator on), fOCO can be used as timer RA. When the FRA00 bit is set to 1, fOCO40M can be used as timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the watchdog timer and voltage detection circuit.
10.5.1.2
Low-Speed Clock Mode
The XCIN clock divided by 1 (no division) provides the CPU clock. In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. When the FRA00 bit is set to 1, fOCO40M can be used as timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the watchdog timer and voltage detection circuit. To enter wait mode from low-speed clock mode, setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.13 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
10.5.1.3
High-Speed On-Chip Oscillator Mode
The high-speed on-chip oscillator is used as the on-chip oscillator clock when the FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The onchip oscillator divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divideby-8 mode) when transiting to high-speed clock mode. If the FRA00 bit is set to 1, fOCO40M can be used as timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used for the watchdog timer and voltage detection circuit.
10.5.1.4
Low-Speed On-Chip Oscillator Mode
If the CM14 bit in the CM1 register is set to 0 (low-speed on-chip oscillator on) or the FRA01bit in the FRA0 register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillator clock. The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8 mode) when transiting to high-speed clock mode. When the FRA00 bit is set to 1, fOCO40M can be used as timer RD. When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer and voltage detection circuit. In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4 register to 1 (flash memory low consumption current read mode enabled) enables low consumption operation. To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1 (internal power low consumption enabled) enables lower consumption current in wait mode. When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.13 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 88 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.5.2
Wait Mode
Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog timer, when count source protection mode is disabled, stop. The XIN clock, XCIN clock, and on-chip oscillator clock do not stop and the peripheral functions using these clocks continue operating.
10.5.2.1
Peripheral Function Clock Stop Function
If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1, f2, f4, f8, and f32 clocks stop in wait mode. This reduces power consumption.
10.5.2.2
Entering Wait Mode
The MCU enters wait mode when the WAIT instruction is executed. When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1 bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT instruction. If the MCU enters wait mode while the OCD1 bit is set to 1 (oscillation stop detection interrupt enabled), current consumption is not reduced because the CPU clock does not stop.
10.5.2.3
Pin Status in Wait Mode
The I/O port is the status before wait mode was entered is maintained.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 89 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.5.2.4
Exiting Wait Mode
The MCU exits wait mode by a reset or a peripheral function interrupt. The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip oscillator clock can be used to exit wait mode. Table 10.3 lists Interrupts to Exit Wait Mode and Usage Conditions. Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions
CM02 = 0 CM02 = 1 Usable when operating with internal Usable when operating with external or external clock clock Clock synchronous serial I/O Usable in all modes (Do not use) with chip select interrupt / I2C bus interface interrupt Key input interrupt Usable Usable A/D conversion interrupt Usable in one-shot mode (Do not use) Timer RA interrupt Usable in all modes Can be used if there is no filter in event counter mode. Usable by selecting fOCO or fC32 as count source. Timer RB interrupt Usable in all modes (Do not use) Timer RD interrupt Usable in all modes Usable by selecting fOCO40M as count source Timer RE interrupt Usable in all modes Usable when operating in real time clock mode Usable INT interrupt Usable (INT0 to INT3 can be used if Voltage monitor 1 interrupt Voltage monitor 2 interrupt Oscillation stop detection interrupt Usable Usable Usable there is no filter.) Usable Usable (Do not use)
Interrupt Serial interface interrupt
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 90 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
Figure 10.12 shows the Time from Wait Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT instruction. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 in the interrupt control registers of the peripheral function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting wait mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operate the peripheral function to be used for exiting wait mode. When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register and the CM07 bit in the CM0 register, as described in Figure 10.12. The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock when the WAIT instruction is executed.
FMR0 Register FMSTP Bit 0 (flash memory operates)
CM0 Register CM07 Bit 0 (system clock) 1 (XCIN clock) 0 (system clock) 1 (XCIN clock)
Time until Flash Memory is Activated (T1) Period of system clock x 12 cycles + 30 s (max.) Period of XCIN clock x 12 cycles + 30 s (max.) Period of system clock x 12 cycles Period of XCIN clock x 12 cycles
Time until CPU Clock is Supplied (T2) Period of CPU clock x 6 cycles Same as above Same as above Same as above
Time for Interrupt Sequence (T3) Period of CPU clock x 20 cycles Same as above Same as above Same as above
Remarks
1 (flash memory stops)
Following total time is the time from wait mode until an interrupt routine is executed.
T1 Flash memory activation sequence Interrupt request generated
T2
T3
Wait mode
CPU clock restart sequence
Interrupt sequence
Figure 10.12
Time from Wait Mode to Interrupt Routine Execution
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 91 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.5.2.5
Reducing Internal Power Consumption
Internal power consumption can be reduced by using low-speed clock mode or low-speed on-chip oscillator mode. Figure 10.13 shows the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit. When enabling reduced internal power consumption using the VCA20 bit, follow Figure 10.13 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
Exit wait mode by interrupt Handling procedure of internal power low consumption enabled by VCA20 bit
(Note 1)
In interrupt routine
Step (1)
Enter low-speed clock mode or low-speed on-chip oscillator mode
Step (5)
VCA20 0 (internal power low consumption disabled)(2)
Step (2)
Stop XIN clock and high-speed on-chip oscillator clock
Step (6)
Start XIN clock or high-speed on-chip oscillator clock
Step (3)
VCA20 1 (internal power low consumption enabled)(2, 3)
Step (7)
(Wait until XIN clock oscillation stabilizes)
If it is necessary to start the high-speed clock or the high-speed on-chip oscillator in the interrupt routine, execute steps (5) to (7) in the interrupt routine.
Step (4)
Enter wait mode(4)
Step (8)
Enter high-speed clock mode or high-speed on-chip oscillator mode
Step (5)
VCA20 0 (internal power low consumption disabled)(2)
Interrupt handling
Step (6)
Start XIN clock or high-speed on-chip oscillator clock
Step (1)
Enter low-speed clock mode or low-speed on-chip oscillator mode If the high-speed clock or high-speed on-chip oscillator is started in the interrupt routine, execute steps (1) to (3) at the last of the interrupt routine.
Step (2) Step (7) (Wait until XIN clock oscillation stabilizes)
Stop XIN clock and high-speed on-chip oscillator clock
Step (8)
Enter high-speed clock mode or high-speed on-chip oscillator mode
Step (3)
VCA20 1 (internal power low consumption enabled)(2, 3)
Interrupt handling completed NOTES: 1. Execute this routine to handle all interrupts generated in wait mode. However, this does not apply if it is not necessary to start the high-speed clock or high-speed on-chip oscillator during the interrupt routine. 2. Do not set the VCA20 bit to 0 with the instruction immediately after setting the VCA20 bit to 1. Also, do not do the opposite. 3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode). 4. When entering wait mode, follow 10.7.2 Wait Mode. VCA20: Bit in VCA2 register
Figure 10.13
Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 92 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.5.3
Stop Mode
Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is maintained. The peripheral functions clocked by external signals continue operating. Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions. Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions Usage Conditions - Can be used if there is no filter Can be used if there is no filter when external pulse is counted in event counter mode When external clock is selected Usable in digital filter disabled mode (VW1C1 bit in VW1C register is set to 1) Usable in digital filter disabled mode (VW2C1 bit in VW2C register is set to 1)
Interrupt Key input interrupt INT0 to INT3 interrupt Timer RA interrupt Serial interface interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt
10.5.3.1
Entering Stop Mode
The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM1 register is set to 1 (XIN clock oscillator circuit drive capacity high). When using stop mode, set bits OCD1 to OCD0 to 00b before entering stop mode.
10.5.3.2
Pin Status in Stop Mode
The status before wait mode was entered is maintained. However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held "H". When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in input status.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 93 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.5.3.3
Exiting Stop Mode
The MCU exits stop mode by a reset or peripheral function interrupt. Figure 10.14 shows the Time from Stop Mode to Interrupt Routine Execution. When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit to 1. (1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for exiting stop mode. Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting stop mode to 000b (interrupt disabled). (2) Set the I flag to 1. (3) Operates the peripheral function to be used for exiting stop mode. When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt request is generated and the CPU clock supply is started. If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral function interrupt, the CPU clock becomes the previous system clock divided by 8.
FMR0 Register FMSTP Bit 0 (flash memory operates) 1 (flash memory stops)
CM0 Register CM07 Bit 0 (system clock) 1 (XCIN clock) 0 (system clock) 1 (XCIN clock)
Time until Flash Memory is Activated (T2) Period of system clock x 12 cycles + 30 s (max.) Period of XCIN clock x 12 cycles + 30 s (max.) Period of system clock x 12 cycles Period of XCIN clock x 12 cycles
Time until CPU Clock is Supplied (T3) Period of CPU clock x 6 cycles Same as above Same as above Same as above
Time for Interrupt Sequence (T4)
Remarks
Period of CPU clock Following total x 20 cycles time of T0 to T4 is the time Same as above from stop mode until an Same as above interrupt handling is Same as above executed.
T0
T1
Oscillation time of before stop mode
T2
T3
T4
Stop mode
Internal power CPU clock source stability time used immediately
Flash memory activation sequence
CPU clock restart sequence
Interrupt sequence
150 s (max.) Interrupt request generated
Figure 10.14
Time from Stop Mode to Interrupt Routine Execution
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 94 of 485
R8C/24 Group, R8C/25 Group Figure 10.15 shows the State Transitions in Power Control Mode.
10. Clock Generation Circuit
State Transitions in Power Control Mode
Reset
Standard operating mode
Low-speed on-chip oscillator mode
CM07 = 0 CM14 = 0 OCD2 = 1 FRA01 = 0
CM14 = 0 OCD2 = 1 FRA01 = 0 CM05 = 0 CM13 = 1 OCD2 = 0
CM04 = 1 CM07 = 1 CM07 = 0 CM14 = 0 OCD2 = 1 FRA01 = 0
FRA00 = 1 FRA01 = 1 CM04 = 1 CM07 = 1
High-speed clock mode
CM05 = 0 CM07 = 0 CM13 = 1 OCD2 = 0
Low-speed clock mode
CM04 = 1 CM07 = 1 CM05 = 0 CM07 = 0 CM13 = 1 OCD2 = 0 CM04 = 1 CM07 = 1
OCD2 = 1 FRA00 = 1 FRA01 = 1 CM05 = 0 CM13 = 1 OCD2 = 0
CM14 = 0 FRA01 = 0
High-speed on-chip oscillator mode
CM07 = 0 OCD2 = 1 FRA00 = 1 FRA01 = 1
CM07 = 0 OCD2 = 1 FRA00 = 1 FRA01 = 1
Interrupt
WAIT instruction
Interrupt
CM10 = 1
Wait mode CPU operation stops CM04, CM05, CM07: Bits in CM0 register CM13, CM14: Bits in CM1 register OCD2: Bit in OCD register FRA00, FRA01: Bits in FRA0 register
Stop mode All oscillators stop
Figure 10.15
State Transitions in Power Control Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 95 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.6
Oscillation Stop Detection Function
The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop detection function can be enabled and disabled by the OCD0 bit in the OCD register. Table 10.5 lists the Specifications of Oscillation Stop Detection Function. When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the system is placed in the following state if the XIN clock stops. * OCD2 bit in OCD register = 1 (on-chip oscillator clock selected) * OCD3 bit in OCD register = 1 (XIN clock stops) * CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates) * Oscillation stop detection interrupt request is generated. Table 10.5 Specifications of Oscillation Stop Detection Function Specification f(XIN) 2 MHz Set bits OCD1 to OCD0 to 11b Oscillation stop detection interrupt is generated
Item Oscillation stop detection clock and frequency bandwidth Enabled condition for oscillation stop detection function Operation at oscillation stop detection
10.6.1
How to Use Oscillation Stop Detection Function
* The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage monitor 2 interrupt, and the watchdog timer interrupt. When using the oscillation stop detection interrupt and watchdog timer interrupt, the interrupt source needs to be determined. Table 10.6 lists the Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts. Figure 10.17 shows an Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt. * When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source of the CPU clock and peripheral functions by a program. Figure 10.16 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN Clock. * To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral function clock does not stop in wait mode). * Since the oscillation stop detection function is a function for cases where the XIN clock is stopped by an external cause, set bits OCD1 to OCD0 to 00b when the XIN clock stops or is started by a program, (stop mode is selected or the CM05 bit is changed). * This function cannot be used when the XIN clock frequency is 2 MHz or below. In this case, set bits OCD1 to OCD0 to 00b. * To use the low-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip oscillator selected) and bits OCD1 to OCD0 to 11b. To use the high-speed on-chip oscillator clock for the CPU clock and clock sources of peripheral functions after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01 bit to 1 (high-speed on-chip oscillator selected) and then set bits OCD1 to OCD0 to 11b.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 96 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
Table 10.6
Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, and Voltage Monitor 2 Interrupts
Generated Interrupt Source Bit Showing Interrupt Cause Oscillation stop detection (a) OCD3 bit in OCD register = 1 ((a) or (b)) (b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1 Watchdog timer VW2C3 bit in VW2C register = 1 Voltage monitor 1 VW1C2 bit in VW1C register = 1 Voltage monitor 2 VW2C2 bit in VW2C register = 1
Switch to XIN clock
NO
Multiple confirmations that OCD3 bit is set to 0 (XIN clock oscillates) ? YES Set OCD1 to OCD0 bits to 00b
Set OCD2 bit to 0 (select XIN clock)
End
OCD3 to OCD0: Bits in OCD register
Figure 10.16
Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN Clock
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 97 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
Interrupt sources judgment
OCD3 = 1 ? (XIN clock stopped)
NO
YES
OCD1 = 1 (oscillation stop detection interrupt enabled) and OCD2 = 1 (on-chip oscillator clock selected as system clock) ?
NO
YES VW2C3 = 1 ? (Watchdog timer underflow) NO
YES VW2C2 = 1 ? (passing Vdet2) NO
YES
Set OCD1 bit to 0 (oscillation stop detection interrupt disabled). (1)
To oscillation stop detection interrupt routine
To watchdog timer interrupt routine
To voltage monitor 2 interrupt routine
To voltage monitor 1 interrupt routine
NOTE: 1. This disables multiple oscillation stop detection interrupts. OCD1 to OCD3: Bits in OCD register VW2C2, VW2C3: Bits in VW2C register
Figure 10.17
Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 98 of 485
R8C/24 Group, R8C/25 Group
10. Clock Generation Circuit
10.7 10.7.1
Notes on Clock Generation Circuit Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit to 1. * Program example to enter stop mode BCLR BSET FSET BSET JMP.B LABEL_001 : NOP NOP NOP NOP
1,FMR0 0,PRCR I 0,CM1 LABEL_001
; CPU rewrite mode disabled ; Protect disabled ; Enable interrupt ; Stop mode
10.7.2
Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction. * Program example to execute the WAIT instruction BCLR 1,FMR0 FSET I WAIT NOP NOP NOP NOP
; CPU rewrite mode disabled ; Enable interrupt ; Wait mode
10.7.3
Oscillation Stop Detection Function
Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set bits OCD1 to OCD0 to 00b.
10.7.4
Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system. To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 99 of 485
R8C/24 Group, R8C/25 Group
11. Protection
11. Protection
The protection function protects important registers from being easily overwritten when a program runs out of control. Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below. * Registers protected by PRC0 bit: Registers CM0, CM1, OCD, FRA0, FRA1, and FRA2 * Registers protected by PRC1 bit: Registers PM0 and PM1 * Registers protected by PRC2 bit: PD0 register * Registers protected by PRC3 bit: Registers VCA2, VW0C, VW1C, and VW2C
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol PRCR Bit Symbol
Address 000Ah Bit Name Protect bit 0
PRC0
After Reset 00h Function Writing to registers CM0, CM1, OCD, FRA0, FRA1, and FRA2 is enabled. 0 : Disables w riting 1 : Enables w riting Writing to registers PM0 and PM1 is enabled. 0 : Disables w riting 1 : Enables w riting Writing to the PD0 register is enabled. 0 : Disables w riting 1 : Enables w riting(1) Writing to registers VCA2, VW0C, VW1C, and VW2C is enabled. 0 : Disables w riting 1 : Enables w riting Set to 0. When read, the content is 0.
RW
RW
Protect bit 1 PRC1 Protect bit 2 PRC2 Protect bit 3 PRC3
RW
RW
RW
-- (b5-b4) -- (b7-b6)
Reserved bits Reserved bits
RW RO
NOTE: 1. This bit is set to 0 after w riting 1 to the PRC2 bit and executing a w rite to any address. Since the other bits are not set to 0, set them to 0 by a program.
Figure 11.1
PRCR Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 100 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12. Interrupts
12.1 12.1.1 Interrupt Overview Types of Interrupts
Figure 12.1 shows the Types of Interrupts.
Software (non-maskable interrupts)
Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Watchdog timer Oscillation stop detection Voltage monitor 1 Voltage monitor 2 Single step(2) Address break(2) Address match
Interrupts Special (non-maskable interrupts) Hardware Peripheral functions(1) (maskable interrupts)
NOTES: 1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts. 2. Do not use this interrupt. This is for use with development tools only.
Figure 12.1
Types of Interrupts
* Maskable Interrupts: * Non-Maskable Interrupts:
The interrupt enable flag (I flag) enables or disables these interrupts. The interrupt priority order can be changed based on the interrupt priority level. The interrupt enable flag (I flag) does not enable or disable these interrupts. The interrupt priority order cannot be changed based on interrupt priority level.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 101 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.2
Software Interrupts
A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.
12.1.2.1
Undefined Instruction Interrupt
The undefined instruction interrupt is generated when the UND instruction is executed.
12.1.2.2
Overflow Interrupt
The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB.
12.1.2.3
BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
12.1.2.4
INT Instruction Interrupt
An INT instruction interrupt is generated when the INT instruction is executed. The INT instruction can select software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function interrupt. Therefore, the MCU executes the same interrupt routine when the INT instruction is executed as when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 102 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.3
Special Interrupts
Special interrupts are non-maskable.
12.1.3.1
Watchdog Timer Interrupt
The watchdog timer interrupt is generated by the watchdog timer. For details, refer to 13. Watchdog Timer.
12.1.3.2
Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt is generated by the oscillation stop detection function. For details of the oscillation stop detection function, refer to 10. Clock Generation Circuit.
12.1.3.3
Voltage Monitor 1 Interrupt
The voltage monitor 1 interrupt is generated by the voltage detection circuit. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit.
12.1.3.4
Voltage Monitor 2 Interrupt
The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection circuit, refer to 6. Voltage Detection Circuit.
12.1.3.5
Single-Step Interrupt, and Address Break Interrupt
Do not use these interrupts. They are for use by development tools only.
12.1.3.6
Address Match Interrupt
The address match interrupt is generated immediately before executing an instruction that is stored at an address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER1 bit in the AIER register is set to 1 (address match interrupt enable). For details of the address match interrupt, refer to 12.4 Address Match Interrupt.
12.1.4
Peripheral Function Interrupt
The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a maskable interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral functions.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 103 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.5
Interrupts and Interrupt Vectors
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector. Figure 12.2 shows an Interrupt Vector.
MSB
LSB
Vector address (L)
Low address Mid address 0000 High address 0000
Vector address (H)
Figure 12.2 Interrupt Vector
0000
12.1.5.1
Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh. Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code check function. For details, refer to 19.3 Functions to Prevent Rewriting of Flash Memory. Table 12.1 Fixed Vector Tables Vector Addresses Remarks Reference Address (L) to (H) 0FFDCh to 0FFDFh Interrupt on UND R8C/Tiny Series Software instruction Manual 0FFE0h to 0FFE3h Interrupt on INTO instruction 0FFE4h to 0FFE7h If the content of address 0FFE7h is FFh, program execution starts from the address shown by the vector in the relocatable vector table. 0FFE8h to 0FFEBh 12.4 Address Match Interrupt 0FFECh to 0FFEFh 0FFF0h to 0FFF3h 13. Watchdog Timer 10. Clock Generation Circuit 6. Voltage Detection Circuit
Interrupt Source Undefined instruction Overflow BRK instruction
Address match Single step(1) Watchdog timer, Oscillation stop detection, Voltage monitor 1, Voltage monitor 2 Address break(1) (Reserved) Reset
0FFF4h to 0FFF7h 0FFF8h to 0FFFBh 0FFFCh to 0FFFFh 5. Resets
NOTE: 1. Do not use these interrupts. They are for use by development tools only.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 104 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.5.2
Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register. Table 12.2 lists the Relocatable Vector Tables. Table 12.2 Relocatable Vector Tables
Vector Addresses(1) Address (L) to Address (H) +0 to +3 (0000h to 0003h) Software Interrupt Control Interrupt Reference Register Number 0 - R8C/Tiny Series Software Manual 1 to 2 - - 3 to 7 - - 8 TRD0IC 14.3 Timer RD 9 10 11 to 12 13 14 15 TRD1IC TREIC - KUPIC ADIC SSUIC/IICIC 14.4 Timer RE - 12.3 Key Input Interrupt 18. A/D Converter 16.2 Clock Synchronous Serial I/O with Chip Select (SSU), 16.3 I2C bus Interface - 15. Serial Interface
Interrupt Source BRK instruction(3) (Reserved) (Reserved) Timer RD (channel 0) Timer RD (channel 1) Timer RE (Reserved) Key input A/D Clock synchronous serial I/O with chip select / I2C bus interface(2) (Reserved) UART0 transmit UART0 receive UART1 transmit UART1 receive INT2 Timer RA (Reserved) Timer RB INT1 INT3 (Reserved) (Reserved) INT0 (Reserved) (Reserved) Software interrupt(3)
+32 to +35 (0020h to 0023h) +36 to +39 (0024h to 0027h) +40 to +43 (0028h to 002Bh) +52 to +55 (0034h to 0037h) +56 to +59 (0038h to 003Bh) +60 to +63 (003Ch to 003Fh)
+68 to +71 (0044h to 0047h) +72 to +75 (0048h to 004Bh) +76 to +79 (004Ch to 004Fh) +80 to +83 (0050h to 0053h) +84 to +87 (0054h to 0057h) +88 to +91 (0058h to 005Bh) +96 to +99 (0060h to 0063h) +100 to +103 (0064h to 0067h) +104 to +107 (0068h to 006Bh)
16 17 18 19 20 21 22 23 24 25 26 27 28 29
- S0TIC S0RIC S1TIC S1RIC INT2IC TRAIC - TRBIC INT1IC INT3IC - - INT0IC - - -
12.2 INT Interrupt 14.1 Timer RA - 14.2 Timer RB 12.2 INT Interrupt - - 12.2 INT Interrupt - - R8C/Tiny Series Software Manual
+116 to +119 (0074h to 0077h)
30 31 +128 to +131 (0080h to 0083h) to 32 to 63 +252 to +255 (00FCh to 00FFh)
NOTES: 1. These addresses are relative to those in the INTB register. 2. The IICSEL bit in the PMR register switches functions. 3. The I flag does not disable these interrupts.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 105 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.6
Interrupt Control
The following describes enabling and disabling the maskable interrupts and setting the priority for acknowledgement. The explanation does not apply to nonmaskable interrupts. Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register. Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRD0IC, TRD1IC, SSUIC, and IICIC and Figure 12.5 shows the INTiIC Register.
Interrupt Control Register(2)
Symbol TREIC KUPIC ADIC S0TIC S0RIC S1TIC S1RIC TRAIC TRBIC Bit Symbol ILVL0 Address 004Ah 004Dh 004Eh 0051h 0052h 0053h 0054h 0056h 0058h Bit Name Interrupt priority level select bits After Reset XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Function
b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
RW RW
ILVL1
ILVL2 Interrupt request bit
0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Requests no interrupt 1 : Requests interrupt
RW
RW
IR -- (b7-b4)
RW(1) --
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
NOTES: 1. Only 0 can be w ritten to the IR bit. Do not w rite 1. 2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents.
Figure 12.3
Interrupt Control Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 106 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
Interrupt Control Register(1)
Symbol TRD0IC TRD1IC SSUIC/IICIC(2) Bit Symbol ILVL0 Address 0048h 0049h 004Fh After Reset XXXXX000b XXXXX000b XXXXX000b Function
b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
Bit Name Interrupt priority level select bits
RW RW
ILVL1
ILVL2 Interrupt request bit
0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Requests no interrupt 1 : Requests interrupt
RW
RW
IR -- (b7-b4)
RO --
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
NOTES: 1. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents. 2. The IICSEL bit in the PMR register sw itches functions.
Figure 12.4
Registers TRD0IC, TRD1IC, SSUIC, and IICIC
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 107 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
INTi Interrupt Control Register (i=0 to 3)(2)
Symbol INT2IC INT1IC INT3IC INT0IC Bit Symbol ILVL0 Address 0055h 0059h 005Ah 005Dh Bit Name Interrupt priority level select bits After Reset XX00X000b XX00X000b XX00X000b XX00X000b Function
b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
0
RW RW
ILVL1
ILVL2 Interrupt request bit Polarity sw itch bit(4) Reserved bit
0 0 0 : Level 0 (interrupt disable) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0 : Requests no interrupt 1 : Requests interrupt 0 : Selects falling edge 1 : Selects rising edge(3) Set to 0.
RW
RW
IR POL -- (b5) -- (b7-b6)
RW(1) RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
NOTES: 1. Only 0 can be w ritten to the IR bit. (Do not w rite 1.) 2. Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated. Refer to 12.6.5 Changing Interrupt Control Register Contents. 3. If the INTiPL bit in the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge). 4. The IR bit may be set to 1 (requests interrupt) w hen the POL bit is rew ritten. Refer to 12.6.4 Changing Interrupt Sources.
Figure 12.5
INTiIC Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 108 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.6.1
I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabled) enables maskable interrupts. Setting the I flag to 0 (disabled) disables all maskable interrupts.
12.1.6.2
IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (= interrupt not requested). The IR bit can be set to 0 by a program. Do not write 1 to this bit. However, the IR bit operations of the timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt and the I 2 C bus Interface Interrupt are different. Refer to 12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request Sources).
12.1.6.3
Bits ILVL2 to ILVL0 and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0. Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels Enabled by IPL. The following are conditions under which an interrupt is acknowledged: * I flag = 1 * IR bit = 1 * Interrupt priority level > IPL The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Table 12.3
ILVL2 to ILVL0 Bits 000b 001b 010b 011b 100b 101b 110b 111b
Settings of Interrupt Priority Levels
Interrupt Priority Level Priority Order - Level 0 (interrupt disabled) Level 1 Low Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High
Table 12.4
IPL 000b 001b 010b 011b 100b 101b 110b 111b
Interrupt Priority Levels Enabled by IPL
Enabled Interrupt Priority Levels Interrupt level 1 and above Interrupt level 2 and above Interrupt level 3 and above Interrupt level 4 and above Interrupt level 5 and above Interrupt level 6 and above Interrupt level 7 and above All maskable interrupts are disabled
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 109 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.6.4
Interrupt Sequence
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle. However, for the SMOVB, SMOVF, SSTR, or RMPA instruction if an interrupt request is generated while the instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt sequence is performed as indicated below. Figure 12.6 shows the Time Required for Executing Interrupt Sequence. (1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address 00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested).(2) (2) The FLG register is saved to a temporary register(1) in the CPU immediately before entering the interrupt sequence. (3) The I, D and U flags in the FLG register are set as follows: The I flag is set to 0 (interrupts disabled). The D flag is set to 0 (single-step interrupt disabled). The U flag is set to 0 (ISP selected). However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is executed. (4) The CPU's internal temporary register(1) is saved to the stack. (5) The PC is saved to the stack. (6) The interrupt priority level of the acknowledged interrupt is set in the IPL. (7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC. After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt routine.
1 CPU Clock Address Bus Data Bus RD WR
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Address 0000h Interrupt information
Undefined Undefined Undefined
SP-2 SP-1
SP-4
SP-3
SP-3 contents
VEC
VEC contents
VEC+1
VEC+1 contents
VEC+2
VEC+2 contents
PC
SP-2 SP-1 SP-4 contents contents contents
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is ready to acknowledge instructions.
Figure 12.6
Time Required for Executing Interrupt Sequence
NOTES: 1. This register cannot be accessed by the user. 2. Refer to 12.5 Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request Sources) for the IR bit operations of the timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and the I2C bus Interface Interrupt.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 110 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.6.5
Interrupt Response Time
Figure 12.7 shows the Interrupt Response Time. The interrupt response time is the period between an interrupt request generation and the execution of the first instruction in the interrupt routine. The interrupt response time includes the period between interrupt request generation and the completion of execution of the instruction (refer to (a) in Figure 12.7) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in Figure 12.7).
Interrupt request is generated. Interrupt request is acknowledged.
Time
Instruction
(a)
Interrupt sequence
20 cycles (b)
Instruction in interrupt routine
Interrupt response time
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 21 cycles for address match and single-step interrupts.
Figure 12.7
Interrupt Response Time
12.1.6.6
IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the acknowledged interrupt is set in the IPL. When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in the IPL. Table 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged. Table 12.5 IPL Value When Software or Special Interrupt Is Acknowledged Value Set in IPL 7 Not changed
Interrupt Source Watchdog timer, oscillation stop detection, voltage monitor 1, voltage monitor 2, Address break Software, address match, single-step
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 111 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.6.7
Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack. After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register, are saved to the stack, the 16 low-order bits in the PC are saved. Figure 12.8 shows the Stack State Before and After Acknowledgement of Interrupt Request. The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM instruction can save several registers in the register bank being currently used(1) with a single instruction. NOTE: 1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Address
MSB
Stack
LSB
Address
MSB
Stack
LSB
m-4 m-3
m-4 m-3
PCL PCM FLGL FLGH PCH
[SP] New SP value
m-2 m-1 m
m-2 m-1
Previous stack contents Previous stack contents
[SP] SP value before interrupt is generated
m
Previous stack contents Previous stack contents
m+1
m+1
PCH PCM PCL FLGH FLGL
: 4 high-order bits of PC : 8 middle-order bits of PC : 8 low-order bits of PC : 4 high-order bits of FLG : 8 low-order bits of FLG
Stack state before interrupt request is acknowledged
Stack state after interrupt request is acknowledged
NOTE: 1. When executing software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP.
Figure 12.8
Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation, which is performed as part of the interrupt sequence, saved in 8 bits at a time in four steps. Figure 12.9 shows the Register Saving Operation.
Stack
Sequence in which order registers are saved
[SP]-5 [SP]-4 [SP]-3
Address
PCL PCM FLGL FLGH PCH
(3) (4)
Saved, 8 bits at a time
[SP]-2 [SP]-1 (1) (2)
[SP]
Completed saving registers in four operations.
PCH PCM PCL FLGH FLGL
: 4 high-order bits of PC : 8 middle-order bits of PC : 8 low-order bits of PC : 4 high-order bits of FLG : 8 low-order bits of FLG
NOTE: 1. [SP] indicates the initial value of the SP when an interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4. When executing
software number 32 to 63 INT instructions, this SP is specified by the U flag. Otherwise it is ISP.
Figure 12.9
Register Saving Operation
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 112 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.6.8
Returning from an Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have been saved to the stack, are automatically restored. The program, that was running before the interrupt request was acknowledged, starts running again. Restore registers saved by a program in an interrupt routine using the POPM instruction or others before executing the REIT instruction.
12.1.6.9
Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with the higher priority is acknowledged. Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions). However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by hardware, and the higher priority interrupts acknowledged. The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set by hardware. Figure 12.10 shows the Priority Levels of Hardware Interrupts. The interrupt priority does not affect software interrupts. The MCU jumps to the interrupt routine when the instruction is executed.
Reset Address break Watchdog timer Oscillation stop detection Voltage monitor 1 Voltage monitor 2 Peripheral function Single step Address match
High
Low
Figure 12.10
Priority Levels of Hardware Interrupts
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 113 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.1.6.10 Interrupt Priority Judgement Circuit
The interrupt priority judgement circuit selects the highest priority interrupt, as shown in Figure 12.11.
Priority level of interrupt
Level 0 (default value)
Highest
INT3 Timer RB Timer RA INT0 INT1 UART1 receive UART0 receive A/D conversion Timer RE Timer RD0 INT2 UART1 transmit UART0 transmit SSU / I2C bus(1) Key input Timer RD1 IPL Lowest Interrupt request level judgment output signal I flag Address match Watchdog timer Oscillation stop detection Voltage monitor 1 Voltage monitor 2 NOTE: 1. The IICSEL bit in the PMR register switches functions. Interrupt request acknowledged Priority of peripheral function interrupts (if priority levels are same)
Figure 12.11
Interrupt Priority Level Judgement Circuit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 114 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.2 12.2.1
INT Interrupt INTi Interrupt (i = 0 to 3)
The INTi interrupt is generated by an INTi input. When using the INTi interrupt, the INTiEN bit in the INTEN register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the POL bit in the INTiIC register. Inputs can be passed through a digital filter with three different sampling clocks. The INT0 pin is shared with the pulse output forced cutoff of timer RD and the external trigger input of timer RB. Figure 12.12 shows the INTEN Register. Figure 12.13 shows the INTF Register.
External Input Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol INTEN Bit Symbol INT0EN INT0PL INT1EN INT1PL INT2EN INT2PL INT3EN INT3PL
Address 00F9h Bit Name _____ INT0 input enable bit
_____
After Reset 00h Function 0 : Disable 1 : Enable 0 : One edge 1 : Both edges 0 : Disable 1 : Enable 0 : One edge 1 : Both edges 0 : Disable 1 : Enable 0 : One edge 1 : Both edges 0 : Disable 1 : Enable 0 : One edge 1 : Both edges
RW RW RW RW RW RW RW RW RW
INT0 input polarity select bit(1,2)
_____
INT1 input enable bit
_____
INT1 input polarity select bit(1,2)
_____
INT2 input enable bit
_____
INT2 input polarity select bit(1,2)
_____
INT3 input enable bit
_____
INT3 input polarity select bit(1,2)
NOTES: 1. When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling edge). 2. The IR bit in the INTiIC register may be set to 1 (requests interrupt) w hen the INTiPL bit is rew ritten. Refer to 12.6.4 Changing Interrupt Sources.
Figure 12.12
INTEN Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 115 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
_______
INT0 Input Filter Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol INTF Bit Symbol
_____
Address 00FAh Bit Name INT0 input filter select bits
b1 b0
After Reset 00h Function 0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling
RW RW
INT0F0
INT0F1
_____
RW
INT1F0
INT1 input filter select bits
b3 b2
INT1F1
_____
0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling
RW
RW
INT2F0
INT2 input filter select bits
b5 b4
INT2F1
_____
0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling
RW
RW
INT3F0
INT3 input filter select bits
b7 b6
INT3F1
0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling
RW
RW
Figure 12.13
INTF Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 116 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.2.2
INTi Input Filter (i = 0 to 3)
The INTi input contains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF register. The INTi level is sampled every sampling clock cycle and if the sampled input level matches three times, the IR bit in the INTiIC register is set to 1 (interrupt requested). Figure 12.14 shows the Configuration of INTi Input Filter. Figure 12.15 shows an Operating Example of INTi Input Filter.
INTiF1 to INTiF0
f1 f8 f32
= 01b = 10b = 11b Sampling clock INTiEN
Other than INTiF1 to INTiF0 = 00b
INTi Port direction register(1)
Digital filter (input level matches 3x)
INTi interrupt
INTiPL = 0
= 00b
INTiF0, INTiF1: Bits in INTF register INTiEN, INTiPL: Bits in INTEN register i = 0 to 3 NOTE: 1. INT0: Port P4_5 direction register INT1: Port P1_5 direction register when using the P1_5 pin Port P1_7 direction register when using the P1_7 pin INT2: Port P6_6 direction register INT3: Port P6_7 direction register
Both edges detection INTiPL = 1 circuit
Figure 12.14
Configuration of INTi Input Filter
INTi input Sampling timing
IR bit in INTiIC register
Set to 0 by a program This is an operation example when bits INTiF1 to INTiF0 in the INTiF register are set to 01b, 10b, or 11b (digital filter enabled). i = 0 to 3
Figure 12.15
Operating Example of INTi Input Filter
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 117 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.3
Key Input Interrupt
A key input interrupt request is generated by one of the input edges of pins K10 to K13. The key input interrupt can be used as a key-on wake-up function to exit wait or stop mode. The KIiEN (i = 0 to 3) bit in the KIEN register can select whether or not the pins are used as KIi input. The KIiPL bit in the KIEN register can select the input polarity. When inputting "L" to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to K13 is not detected as interrupts. Also, when inputting "H" to the KIi pin, which sets the KIiPL bit to 1 (rising edge), the input of the other pins K10 to K13 is not detected as interrupts. Figure 12.16 shows a Block Diagram of Key Input Interrupt.
PU02 bit in PUR0 register Pull-up transistor KUPIC register PD1_3 bit in PD1 register KI3EN bit PD1_3 bit KI3PL = 0 KI3 KI3PL = 1 Pull-up transistor KI2 KI2PL = 1 Pull-up transistor KI1 KI1PL = 1 Pull-up transistor KI0 KI0PL = 1 KI0EN bit PD1_0 bit KI0PL = 0 KI0EN, KI1EN, KI2EN, KI3EN, KI0PL, KI1PL, KI2PL, KI3PL: Bits in KIEN register PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 register KI1EN bit PD1_1 bit KI1PL = 0 KI2EN bit PD1_2 bit KI2PL = 0 Interrupt control circuit Key input interrupt request
Figure 12.16
Block Diagram of Key Input Interrupt
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 118 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
Key Input Enable Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KIEN Bit Symbol KI0EN KI0PL KI1EN KI1PL KI2EN KI2PL KI3EN KI3PL
Address 00FBh Bit Name KI0 input enable bit KI0 input polarity select bit KI1 input enable bit KI1 input polarity select bit KI2 input enable bit KI2 input polarity select bit KI3 input enable bit KI3 input polarity select bit
After Reset 00h Function 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge 0 : Disable 1 : Enable 0 : Falling edge 1 : Rising edge
RW RW RW RW RW RW RW RW RW
NOTE: 1. The IR bit in the KUPIC register may be set to 1 (requests interrupt) w hen the KIEN register is rew ritten. Refer to 12.6.4 Changing Interrupt Sources.
Figure 12.17
KIEN Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 119 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.4
Address Match Interrupt
An address match interrupt request is generated immediately before execution of the instruction at the address indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and fixed vector tables) in a user system. Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt. The value of the PC (Refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when an address match interrupt is acknowledged varies depending on the instruction at the address indicated by the RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match interrupt, return by one of the following means: * Change the content of the stack and use the REIT instruction. * Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged. Then use a jump instruction. Table 12.6 lists the Values of PC Saved to Stack when Address Match Interrupt is Acknowledged. Figure 12.18 shows Registers AIER and RMAD0 to RMAD1. Table 12.6 Values of PC Saved to Stack when Address Match Interrupt is Acknowledged Address Indicated by RMADi Register (i = 0 or 1) * Instruction with 2-byte operation * Instruction with 1-byte operation code(2) ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ STNZ #IMM8,dest STZX #IMM81,#IMM82,dest CMP.B:S #IMM8,dest PUSHM src POPM JMPS #IMM8 JSRS #IMM8 MOV.B:S #IMM,dest (however, dest = A0 or A1) * Instructions other than the above code(2) PC Value Saved(1) Address indicated by RMADi register + 2 #IMM8,dest #IMM8,dest dest
Address indicated by RMADi register + 1
NOTES: 1. Refer to the 12.1.6.7 Saving a Register for the PC value saved. 2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001). Chapter 4. Instruction Code/Number of Cycles contains diagrams showing operation code below each syntax. Operation code is shown in the bold frame in the diagrams. Table 12.7 Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register Address match interrupt 0 AIER0 RMAD0 Address match interrupt 1 AIER1 RMAD1
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 120 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit Symbol AIER0 AIER1 -- (b7-b2)
Address 0013h Bit Name Address match interrupt 0 enable bit 0 : Disable 1 : Enable Address match interrupt 1 enable bit 0 : Disable 1 : Enable Nothing is assigned. If necessary, set to 0. When read, the content is 0.
After Reset 00h Function
RW RW RW --
Address Match Interrupt Register i (i = 0 or 1)
(b23) b7 (b19) b3 (b16) (b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1 Function
Address 0012h-0010h 0016h-0014h
After Reset 000000h 000000h Setting Range 00000h to FFFFFh RW RW --
Address setting register for address match interrupt -- Nothing is assigned. If necessary, set to 0. (b7-b4) When read, the content is 0.
Figure 12.18
Registers AIER and RMAD0 to RMAD1
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 121 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.5
Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupts, and I2C bus Interface Interrupt (Interrupts with Multiple Interrupt Request Sources)
The timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock synchronous serial I/O with chip select interrupt, and I2C bus interface interrupt each have multiple interrupt request sources. An interrupt request is generated by the logical OR of several interrupt request factors and is reflected in the IR bit in the corresponding interrupt control register. Therefore, each of these peripheral functions has its own interrupt request source status register (status register) and interrupt request source enable register (enable register) to control the generation of interrupt requests (change the IR bit in the interrupt control register). Table 12.8 lists the Registers Associated with Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and I2C bus Interface Interrupt and Figure 12.19 shows a Block Diagram of Timer RD Interrupt. Table 12.8 Registers Associated with Timer RD Interrupt, Clock Synchronous Serial I/O with Chip Select Interrupt, and I2C bus Interface Interrupt Enable Register of Interrupt Control Interrupt Request Source Register TRDIER0 TRD0IC TRDIER1 TRD1IC SSER SSUIC ICIER IICIC
Status Register of Interrupt Request Source Timer RD Channel 0 TRDSR0 Channel 1 TRDSR1 Clock synchronous serial SSSR I/O with chip select ICSR I2C bus interface
Channel i
IMFA bit IMIEA bit IMFB bit IMIEB bit IMFC bit IMIEC bit IMFD bit IMIED bit UDF bit OVF bit OVIE bit Timer RD (channel i) interrupt request (IR bit in TRDiIC register)
i = 0 or 1 IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
Figure 12.19
Block Diagram of Timer RD Interrupt
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 122 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
As with other maskable interrupts, the timer RD (channel 0) interrupt, timer RD (channel 1) interrupt, clock synchronous serial I/O with chip select interrupt, and I2C bus interface interrupt are controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since each interrupt source is generated by a combination of multiple interrupt request sources, the following differences from other maskable interrupts apply: * When bits in the enable register corresponding to bits set to 1 in the status register are set to 1 (enable interrupt), the IR bit in the interrupt control register is set to 1 (interrupt requested). * When either bits in the status register or bits in the enable register corresponding to bits in the status register, or both, are set to 0, the IR bit is set to 0 (interrupt not requested). Basically, even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. Also, the IR bit is not set to 0 even if 0 is written to the IR bit. * Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged. Therefore, the IR bit is also not automatically set to 0 when the interrupt is acknowledged. Set each bit in the status register to 0 in the interrupt routine. Refer to the status register figure for how to set individual bits in the status register to 0. * When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set to 1, the IR bit remains 1. * When multiple bits in the enable register are set to 1, determine by the status register which request source causes an interrupt. Refer to chapters of the individual peripheral functions (14.3 Timer RD, 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) and 16.3 I2C bus Interface) for the status register and enable register. Refer to 12.1.6 Interrupt Control for the interrupt control register.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 123 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.6 12.6.1
Notes on Interrupts Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be generated.
12.6.2
SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an interrupt is acknowledged before setting a value in the SP, the program may run out of control.
12.6.3
External Interrupt and Key Input Interrupt
Either "L" level or an "H" level of width shown in the Electrical Characteristics is necessary for the signal input to pins INT0 to INT3 and pins KI0 to KI3, regardless of the CPU clock. For details, refer to Table 20.21 (VCC = 5V), Table 20.27 (VCC = 3V), Table 20.33 (VCC = 2.2V) External Interrupt INTi (i = 0 to 3) Input.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 124 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.6.4
Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after the change. Refer to the individual peripheral function for its related interrupts. Figure 12.20 shows an Example of Procedure for Changing Interrupt Sources.
Interrupt source change
Disable interrupts(2, 3)
Change interrupt source (including mode of peripheral function)
Set the IR bit to 0 (interrupt not requested) using the MOV instruction(3)
Enable interrupts (2, 3)
Change completed
IR bit:
The interrupt control register bit of an interrupt whose source is changed.
NOTES: 1. Execute the above settings individually. Do not execute two or more settings at once (by one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 of the interrupt whose source is changed. 3. Refer to 12.6.5 Changing Interrupt Control Register Contents for the instructions to be used and usage notes.
Figure 12.20
Example of Procedure for Changing Interrupt Sources
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 125 of 485
R8C/24 Group, R8C/25 Group
12. Interrupts
12.6.5
Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) When changing the contents of an interrupt control register after disabling interrupts, be careful to choose appropriate instructions. Changing any bit other than IR bit If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a problem, use the following instructions to change the register: AND, OR, BCLR, BSET Changing IR bit If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0. (c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts
Example 2: Use dummy read to delay FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h MOV.W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h POPC FLG ; Enable interrupts
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 126 of 485
R8C/24 Group, R8C/25 Group
13. Watchdog Timer
13. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows selection of count source protection mode enable or disable. Table 13.1 lists information on the Count Source Protection Mode. Refer to 5.6 Watchdog Timer Reset for details on the watchdog timer. Figure 13.1 shows the Block Diagram of Watchdog Timer. Figure 13.2 shows the Registers OFS and WDC, Figure 13.3 shows Registers WDTR, WDTS, and CSPR. Table 13.1 Count Source Protection Mode Item Count source Count operation Count start condition Count Source Protection Mode Disabled CPU clock Count Source Protection Mode Enabled Low-speed on-chip oscillator clock
Decrement Either of the following can be selected * After reset, count starts automatically * Count starts by writing to WDTS register Count stop condition Stop mode, wait mode None Reset condition of watchdog * Reset timer * Write 00h to the WDTR register before writing FFh * Underflow Watchdog timer reset Operation at the time of underflow Watchdog timer interrupt or watchdog timer reset
Prescaler
1/16 1/128 CPU clock 1/2
CM07 = 0, WDC7 = 0 CSPRO = 0 CM07 = 0, WDC7 = 1 CM07 = 1 PM12 = 0 Watchdog timer interrupt request
Watchdog timer
PM12 = 1 Watchdog timer reset
fOCO-S
CSPRO = 1 Set to 7FFFh(1)
Write to WDTR register Internal reset signal ("L" active)
NOTE: 1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
CSPRO: Bit in CSPR register WDC7: Bit in WDC register PM12: Bit in PM1 register CM07: Bit in CM0 register
Figure 13.1
Block Diagram of Watchdog Timer
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 127 of 485
R8C/24 Group, R8C/25 Group
13. Watchdog Timer
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol OFS Bit Symbol WDTON -- (b1) ROMCR ROMCP1 -- (b4)
Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Voltage detection 0 circuit start bit(2)
When Shipping FFh(3) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. 0 : Voltage monitor 0 reset enabled after hardw are reset 1 : Voltage monitor 0 reset disabled after hardw are reset Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset
RW RW RW RW RW RW
LVD0ON
RW
-- (b6)
Reserved bit
RW
Count source protect CSPROINI mode after reset select bit
RW
NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after reset). 3. If the block including the OFS register is erased, FFh is set to the OFS register.
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol Address 000Fh WDC Bit Symbol Bit Name -- High-order bits of w atchdog timer (b4-b0) -- (b5) -- (b6) WDC7 Reserved bit Reserved bit Prescaler select bit
After Reset 00X11111b Function
RW RO RW RW RW
Set to 0. When read, the content is undefined. Set to 0. 0 : Divide-by-16 1 : Divide-by-128
Figure 13.2
Registers OFS and WDC
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 128 of 485
R8C/24 Group, R8C/25 Group
13. Watchdog Timer
Watchdog Timer Reset Register
b7 b0
Symbol WDTR
Address 000Dh
After Reset Undefined RW
Function When 00h is w ritten before w riting FFh, the w atchdog timer is reset.(1) The default value of the w atchdog timer is 7FFFh w hen count source protection mode is disabled and 0FFFh w hen count source protection mode is enabled.(2) NOTES: 1. Do not generate an interrupt betw een w hen 00h and FFh are w ritten. 2. When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled), 0FFFh is set in the w atchdog timer.
WO
Watchdog Timer Start Register
b7 b0
Symbol WDTS
Address 000Eh
After Reset Undefined RW WO
Function The w atchdog timer starts counting after a w rite instruction to this register.
Count Source Protection Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0000000
Symbol Address 001Ch CSPR Bit Symbol Bit Name Reserved bits -- (b6-b0) CSPRO
After Reset(1) 00h Function Set to 0.
RW RW RW
Count source protection mode 0 : Count source protection mode disabled select bit(2) 1 : Count source protection mode enabled
NOTES: 1. When 0 is w ritten to the CSPROINI bit in the OFS register, the value after reset is 10000000b. 2. Write 0 before w riting 1 to set the CSPRO bit to 1. 0 cannot be set by a program.
Figure 13.3
Registers WDTR, WDTS, and CSPR
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 129 of 485
R8C/24 Group, R8C/25 Group
13. Watchdog Timer
13.1
Count Source Protection Mode Disabled
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled. Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled). Table 13.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled) Item Count source Count operation Period CPU clock Decrement Division ratio of prescaler (n) x count value of watchdog timer (32768)(1) CPU clock n: 16 or 128 (selected by WDC7 bit in WDC register) Example: When the CPU clock frequency is 16 MHz and prescaler divided by 16, the period is approximately 32.8 ms The WDTON bit(2) in the OFS register (0FFFFh) selects the operation of the watchdog timer after a reset * When the WDTON bit is set to 1 (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register is written to * When the WDTON bit is set to 0 (watchdog timer starts automatically after exiting) The watchdog timer and prescaler start counting automatically after a reset * Reset * Write 00h to the WDTR register before writing FFh * Underflow Stop and wait modes (inherit the count from the held value after exiting modes) * When the PM12 bit in the PM1 register is set to 0 Watchdog timer interrupt * When the PM12 bit in the PM1 register is set to 1 Watchdog timer reset (refer to 5.6 Watchdog Timer Reset) Specification
Count start condition
Reset condition of watchdog timer Count stop condition Operation at time of underflow
NOTES: 1. The watchdog timer is reset when 00h is written to the WDTR register before FFh. The prescaler is reset after the MCU is reset. Some errors in the period of the watchdog timer may be caused by the prescaler. 2. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address 0FFFFh with a flash programmer.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 130 of 485
R8C/24 Group, R8C/25 Group
13. Watchdog Timer
13.2
Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the watchdog timer. Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled). Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled) Item Count source Count operation Period Specification Low-speed on-chip oscillator clock Decrement Count value of watchdog timer (4096) Low-speed on-chip oscillator clock Example: Period is approximately 32.8 ms when the low-speed onchip oscillator clock frequency is 125 kHz The WDTON bit(1) in the OFS register (0FFFFh) selects the operation of the watchdog timer after a reset. * When the WDTON bit is set to 1 (watchdog timer is in stop state after reset) The watchdog timer and prescaler stop after a reset and the count starts when the WDTS register is written to * When the WDTON bit is set to 0 (watchdog timer starts automatically after reset) The watchdog timer and prescaler start counting automatically after a reset * Reset * Write 00h to the WDTR register before writing FFh * Underflow None (The count does not stop in wait mode after the count starts. The MCU does not enter stop mode.) Watchdog timer reset (Refer to 5.6 Watchdog Timer Reset.) * When setting the CSPPRO bit in the CSPR register to 1 (count source protection mode is enabled)(2), the following are set automatically - Set 0FFFh to the watchdog timer - Set the CM14 bit in the CM1 register to 0 (low-speed on-chip oscillator on) - Set the PM12 bit in the PM1 register to 1 (The watchdog timer is reset when watchdog timer underflows) * The following conditions apply in count source protection mode - Writing to the CM10 bit in the CM1 register is disabled (It remains unchanged even if it is set to 1. The MCU does not enter stop mode.) - Writing to the CM14 bit in the CM1 register is disabled (It remains unchanged even if it is set to 1. The low-speed on-chip oscillator does not stop.)
Count start condition
Reset condition of watchdog timer Count stop condition Operation at time of underflow Registers, bits
NOTES: 1. The WDTON bit cannot be changed by a program. To set the WDTON bit, write 0 to bit 0 of address 0FFFFh with a flash programmer. 2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The CSPROINI bit cannot be changed by a program. To set the CSPROINI bit, write 0 to bit 7 of address 0FFFFh with a flash programmer.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 131 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14. Timers
The MCU has two 8-bit timers with 8-bit prescalers, two 16-bit timers, and a timer with a 4-bit counter and an 8-bit counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to store the default value of the counter. The 16-bit timer is timer RD, and has input capture and output compare functions. The 4 and 8-bit counters are timer RE, and has an output compare function. All the timers operate independently. Table 14.1 lists Functional Comparison of Timers.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 132 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.1
Functional Comparison of Timers
Timer RA 8-bit timer with 8bit prescaler (with reload register) Decrement * f1 * f2 * f8 * fOCO * fC32 Timer RB 8-bit timer with 8bit prescaler (with reload register) Decrement * f1 * f2 * f8 * Timer RA underflow Timer RD 16-bit free-run timer x 2 (with input capture and output compare) Increment/Decrement * f1 * f2 * f4 * f8 * f32 * fOCO40M * TRDIOA0 Provided (input capture function, output compare function) Not provided Not provided Not provided Not provided Not provided Timer RE 4-bit counter 8-bit counter Increment * f4 * f8 * f32 * fC4
Item Configuration
Count Count sources
Function Timer mode
Provided
Provided
Not provided
Pulse output mode Event counter mode Pulse width measurement mode Pulse period measurement mode Programmable waveform generation mode Programmable oneshot generation mode Programmable wait one-shot generation mode Input capture mode Output compare mode PWM mode Reset synchronized PWM mode Complementary PWM mode PWM3 mode Real-time clock mode Input pin
Provided Provided Provided Provided Not provided
Not provided Not provided Not provided Not provided Provided
Not provided Not provided Not provided Not provided Not provided
Not provided
Provided
Not provided
Not provided
Not provided
Provided
Not provided
Not provided
Not provided Not provided Not provided Not provided Not provided Not provided Not provided TRAIO
Not provided Not provided Not provided Not provided Not provided Not provided Not provided INT0
Provided Provided Provided Provided Provided Provided Not provided
Not provided Provided Not provided Not provided Not provided Not provided Provided -
Output pin
Related interrupt
Timer stop
INT0, TRDCLK, TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 TRAO TRBO TRDIOA0, TRDIOA1, TRAIO TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 Timer RA interrupt Timer RB interrupt Compare match/input INT1 interrupt INT0 interrupt Capture A0 to D0 interrupt Compare match/input Capture A1 to D1 interrupt Overflow interrupt Underflow interrupt(1) INT0 interrupt Provided Provided Provided
TREO
Timer RE interrupt
Provided
NOTE: 1. The underflow interrupt can be set to channel 1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 133 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.1
Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 14.2 to 14.6 the Specifications of Each Mode). The count source for timer RA is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 14.1 shows a Block Diagram of Timer RA. Figures 14.2 and 14.3 show the registers associated with Timer RA. Timer RA has the following five operating modes: * Timer mode: The timer counts the internal count source. * Pulse output mode: The timer counts the internal count source and outputs pulses of which polarity inverted by underflow of the timer. * Event counter mode: The timer counts external pulses. * Pulse width measurement mode: The timer measures the pulse width of an external pulse. * Pulse period measurement mode: The timer measures the pulse period of an external pulse.
Data bus TCK2 to TCK0 bit f1 f8 fOCO f2 fC32
= 000b = 001b = 010b = 011b = 100b
TCKCUT bit
TMOD2 to TMOD0 = other than 010b
Reload register TCSTF bit Counter
Reload register Underflow signal Timer RA interrupt
TIPF1 to TIPF0 bits f1 = 10b f8 = 11b f32
= 01b
TMOD2 to TMOD0 = 010b
TRAPRE register (prescaler)
Counter TRA register (timer)
TIPF1 to TIPF0 bits TIOSEL = 0 = other than Digital 000b INT1/TRAIO (P1_7) pin
TMOD2 to TMOD0 = 011b or 100b Polarity switching Count control circle
filter
INT1/TRAIO (P1_5) pin
TIOSEL = 1
= 00b
Measurement completion signal
TMOD2 to TMOD0 = 001b TEDGSEL = 1 TOPCR bit Q
Toggle flip-flop CK
TOENA bit TRAO pin
Q TEDGSEL = 0
CLR
Write to TRAMR register Write 1 to TSTOP bit TCSTF, TSTOP: Bits in TRACR register TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF0: Bits in TRAIOC register TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: Bits in TRAMR register
Figure 14.1
Block Diagram of Timer RA
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 134 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RA Control Register(4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRACR Bit Symbol TSTART TCSTF TSTOP -- (b3) TEDGF
Address 0100h Bit Name Timer RA count start bit(1) Timer RA count status flag(1) Timer RA count forcible stop bit(2)
After Reset 00h Function 0 : Count stops 1 : Count starts 0 : Count stops 1 : During count When this bit is set to 1, the count is forcibly stopped. When read, its content is 0.
RW RW RO RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Active edge judgment flag(3, 5) Timer RA underflow flag(3, 5) 0 : Active edge not received 1 : Active edge received (end of measurement period) 0 : No underflow 1 : Underflow
RW
TUNDF -- (b7-b6)
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NOTES: 1. Refer to 14.1.6 Notes on Tim er RA. 2. When the TSTOP bit is set to 1, bits TSTART and TCSTF and registers TPRAPRE and TRA are set to the values after a reset. 3. Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program. How ever, their value remains unchanged w hen 1 is w ritten. 4. In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR register. If it is necessary to avoid changing the values of bits TEDGF and TUNDF, w rite 1 to them. 5. Set to 0 in timer mode, pulse output mode, and event counter mode.
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 -- (b7-b6)
Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit
_____
After Reset 00h Function Function varies depending on operating mode.
RW RW RW RW RW RW --
INT1/TRAIO select bit TRAIO input filter select bits Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Figure 14.2
Registers TRACR and TRAIOC
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 135 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RA Mode Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRAMR Bit Symbol TMOD0
Address 0102h Bit Name Timer RA operating mode select bits
After Reset 00h Function
b2 b1 b0
RW RW
TMOD1
TMOD2 -- (b3) TCK0
0 0 0 : Timer mode 0 0 1 : Pulse output mode 0 1 0 : Event counter mode 0 1 1 : Pulse w idth measurement mode 1 0 0 : Pulse period measurement mode 101: 1 1 0 : Do not set. 111:
RW
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RA count source select bits
b6 b5 b4
--
TCK1
TCK2 Timer RA count source cutoff bit
0 0 0 : f1 0 0 1 : f8 0 1 0 : fOCO 0 1 1 : f2 1 0 0 : fC32 101: 1 1 0 : Do not set. 111: 0 : Provides count source 1 : Cuts off count source
RW
RW
RW
TCKCUT
RW
NOTE: 1. When both the TSTART and TCSTF bits in the TRACR register are set to 0 (count stops), rew rite this register.
Timer RA Prescaler Register
b7 b0
Symbol TRAPRE Mode Timer mode Pulse output mode Event counter mode Pulse w idth measurement mode Pulse period measurement mode
Counts Counts Counts Counts
Address 0103h Function an internal count source an internal count source an external count source internal count source
After Reset FFh(1) Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh 00h to FFh
RW RW RW RW RW RW
NOTE: 1. When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.
Timer RA Register
b7 b0
Symbol TRA Mode All modes
Address 0104h Function Counts on underflow of timer RA prescaler register
After Reset FFh(1) Setting Range 00h to FFh
RW RW
NOTE: 1. When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.
Figure 14.3
Registers TRAMR, TRAPRE, and TRA Page 136 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
14. Timers
14.1.1
Timer Mode
In this mode, the timer counts an internally generated count source (refer to Table 14.2 Timer Mode Specifications). Figure 14.4 shows the TRAIOC Register in Timer Mode. Table 14.2 Timer Mode Specifications Specification f1, f2, f8, fOCO, fC32 * Decrement * When the timer underflows, the contents of the reload register are reloaded and the count is continued. 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register 1 (count starts) is written to the TSTART bit in the TRACR register. * 0 (count stops) is written to the TSTART bit in the TRACR register. * 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. When timer RA underflows [timer RA interrupt]. Programmable I/O port, or INT1 interrupt input Programmable I/O port The count value can be read by reading registers TRA and TRAPRE. * When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. * When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation).
Item Count sources Count operations
Divide ratio Count start condition Count stop conditions Interrupt request generation timing INT1/TRAIO pin function TRAO pin function Read from timer Write to timer
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
000
Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 -- (b7-b6)
Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit
_____
After Reset 00h Function Set to 0 in timer mode.
RW RW RW RW
_____
0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) TRAIO input filter select bits Set to 0 in timer mode. Nothing is assigned. If necessary, set to 0. When read, the content is 0.
INT1/TRAIO select bit
RW RW --
Figure 14.4
TRAIOC Register in Timer Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 137 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.1.1.1
Timer Write Control during Count Operation
Timer RA has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the reload register and counter. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count operation is in progress, the counter value is not updated immediately after the WRITE instruction is executed. Figure 14.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count Operation.
Set 01h to the TRAPRE register and 25h to the TRA register by a program.
Count source
After writing, the reload register is written to at the first count source. Reloads register of timer RA prescaler Previous value Reload at second count source Counter of timer RA prescaler 06h 05h 04h 01h 00h New value (01h) Reload at underflow 01h 00h 01h 00h 01h 00h
After writing, the reload register is written to at the first underflow. Reloads register of timer RA Previous value New value (25h) Reload at the second underflow Counter of timer RA 03h 02h 25h 24h
IR bit in TRAIC register
0 The IR bit remains unchanged until underflow is generated by a new value.
The above applies under the following conditions. Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).
Figure 14.5
Operating Example of Timer RA when Counter Value is Rewritten during Count Operation
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 138 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.1.2
Pulse Output Mode
In pulse output mode, the internally generated count source is counted, and a pulse with inverted polarity is output from the TRAIO pin each time the timer underflows (refer to Table 14.3 Pulse Output Mode Specifications). Figure 14.6 shows the TRAIOC Register in Pulse Output Mode. Table 14.3 Pulse Output Mode Specifications Specification
f1, f2, f8, fOCO, fC32 * Decrement * When the timer underflows, the contents in the reload register is reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: Value set in TRAPRE register, m: Value set in TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions * 0 (count stops) is written to the TSTART bit in the TRACR register. * 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. When timer RA underflows [timer RA interrupt]. Interrupt request generation timing INT1/TRAIO pin function TRAO pin function Read from timer Write to timer Pulse output, programmable output port, or INT1 interrupt(1) Programmable I/O port or inverted output of TRAIO(1) The count value can be read by reading registers TRA and TRAPRE. * When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. * When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). * TRAIO output polarity switch function The TEDGSEL bit in the TRAIOC register selects the level at the start of pulse output.(1) * TRAO output function Pulses inverted from the TRAIO output polarity can be output from the TRAO pin (selectable by the TOENA bit in the TRAIOC register). * Pulse output stop function Output from the TRAIO pin is stopped by the TOPCR bit in the TRAIOC register. * INT1/TRAIO pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
Item Count sources Count operations
Select functions
NOTE: 1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR register is written to.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 139 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL TIPF0 TIPF1 -- (b7-b6)
Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit
_____
After Reset 00h Function 0 : TRAIO output starts at "H" 1 : TRAIO output starts at "L" 0 : TRAIO output 1 : Port P1_7 or P1_5 0 : Port P3_0 1 : TRAO output (inverted TRAIO output from P3_0)
_____
RW RW RW RW RW RW RW --
INT1/TRAIO select bit
0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5) TRAIO input filter select bits Set to 0 in pulse output mode. Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Figure 14.6
TRAIOC Register in Pulse Output Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 140 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.1.3
Event Counter Mode
In event counter mode, external signal inputs to the INT1/TRAIO pin are counted (refer to Table 14.4 Event Counter Mode Specifications). Figure 14.7 shows the TRAIOC Register in Event Counter Mode. Table 14.4 Event Counter Mode Specifications
Specification External signal which is input to TRAIO pin (active edge selectable by a program) * Decrement * When the timer underflows, the contents of the reload register are reloaded and the count is continued. Divide ratio 1/(n+1)(m+1) n: setting value of TRAPRE register, m: setting value of TRA register Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register. Count stop conditions * 0 (count stops) is written to the TSTART bit in the TRACR register. * 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. Interrupt request * When timer RA underflows [timer RA interrupt]. generation timing INT1/TRAIO pin function TRAO pin function Read from timer Write to timer Count source input (INT1 interrupt input) Programmable I/O port or pulse output(1) The count value can be read by reading registers TRA and TRAPRE. * When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. * When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). * NT1 input polarity switch function The TEDGSEL bit in the TRAIOC register selects the active edge of the count source. * Count source input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. * Pulse output function Pulses of inverted polarity can be output from the TRAO pin each time the timer underflows (selectable by the TOENA bit in the TRAIOC register).(1) * Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency.
Item Count source Count operations
Select functions
NOTE: 1. The level of the output pulse becomes the level when the pulse output starts when the TRAMR register is written to.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 141 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TRAIOC Bit Symbol
Address 0101h Bit Name TRAIO polarity sw itch bit
TEDGSEL
After Reset 00h Function 0 : Starts counting at rising edge of the TRAIO input or TRAIO starts output at "L" 1 : Starts counting at falling edge of the TRAIO input or TRAIO starts output at "H" Set to 0 in event counter mode. 0 : Port P3_0 1 : TRAO output
_____
RW
RW
TOPCR TOENA TIOSEL
TRAIO output control bit TRAO output enable bit
_____
RW RW RW
INT1/TRAIO select bit TRAIO input filter select bits (1)
0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5)
b5 b4
TIPF0
TIPF1 -- (b7-b6)
0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
--
NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.7
TRAIOC Register in Event Counter Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 142 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.1.4
Pulse Width Measurement Mode
In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is measured (refer to Table 14.5 Pulse Width Measurement Mode Specifications). Figure 14.8 shows the TRAIOC Register in Pulse Width Measurement Mode and Figure 14.9 shows an Operating Example of Pulse Width Measurement Mode. Table 14.5 Pulse Width Measurement Mode Specifications Specification f1, f2, f8, fOCO, fC32 * Decrement * Continuously counts the selected signal only when measurement pulse is "H" level, or conversely only "L" level. * When the timer underflows, the contents of the reload register are reloaded and the count is continued. 1 (count starts) is written to the TSTART bit in the TRACR register. * 0 (count stops) is written to the TSTART bit in the TRACR register. * 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. * When timer RA underflows [timer RA interrupt]. * Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt]
Item Count sources Count operations
Count start condition Count stop conditions Interrupt request generation timing
INT1/TRAIO pin function Measured pulse input (INT1 interrupt input) Programmable I/O port TRAO pin function Read from timer Write to timer The count value can be read by reading registers TRA and TRAPRE. * When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. * When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). * Measurement level select The TEDGSEL bit in the TRAIOC register selects the "H" or "L" level period. * Measured pulse input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. * Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency.
Select functions
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 143 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TRAIOC Bit Symbol TEDGSEL TOPCR TOENA TIOSEL
Address 0101h Bit Name TRAIO polarity sw itch bit TRAIO output control bit TRAO output enable bit
_____
After Reset 00h Function 0 : TRAIO input starts at "L" 1 : TRAIO input starts at "H" Set to 0 in pulse w idth measurement mode.
RW RW RW RW
_____
INT1/TRAIO select bit TRAIO input filter select bits (1)
0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5)
b5 b4
RW
TIPF0
TIPF1 -- (b7-b6)
0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
--
NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.8
TRAIOC Register in Pulse Width Measurement Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 144 of 485
R8C/24 Group, R8C/25 Group
14. Timers
n = high level: the contents of TRA register, low level: the contents of TRAPRE register FFFFh n
Content of counter (hex)
Count start
Underflow
Count stop
Count stop
0000h Set to 1 by program TSTART bit in TRACR register 1 0
Count start
Count start Period
Measured pulse (TRAIO pin input)
1 0 Set to 0 when interrupt request is acknowledged, or set by program
IR bit in TRAIC register
1 0 Set to 0 by program
TEDGF bit in TRACR register
1 0 Set to 0 by program
TUNDF bit in TRACR register
1 0
The above applies under the following conditions. * "H" level width of measured pulse is measured. (TEDGSEL = 1) * TRAPRE = FFh
Figure 14.9
Operating Example of Pulse Width Measurement Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 145 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.1.5
Pulse Period Measurement Mode
In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is measured (refer to Table 14.6 Pulse Period Measurement Mode Specifications). Figure 14.10 shows the TRAIOC Register in Pulse Period Measurement Mode and Figure 14.11 shows an Operating Example of Pulse Period Measurement Mode. Table 14.6 Pulse Period Measurement Mode Specifications Specification f1, f2, f8, fOCO, fC32 * Decrement * After the active edge of the measured pulse is input, the contents of the readout buffer are retained at the first underflow of timer RA prescaler. Then timer RA reloads the contents in the reload register at the second underflow of timer RA prescaler and continues counting. 1 (count starts) is written to the TSTART bit in the TRACR register. * 0 (count stops) is written to TSTART bit in the TRACR register. * 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register. * When timer RA underflows or reloads [timer RA interrupt]. * Rising or falling of the TRAIO input (end of measurement period) [timer RA interrupt]
Item Count sources Count operations
Count start condition Count stop conditions Interrupt request generation timing
INT1/TRAIO pin function Measured pulse input(1) (INT1 interrupt input) Programmable I/O port TRAO pin function Read from timer Write to timer The count value can be read by reading registers TRA and TRAPRE. * When registers TRAPRE and TRA are written while the count is stopped, values are written to both the reload register and counter. * When registers TRAPRE and TRA are written during the count, values are written to the reload register and counter (refer to 14.1.1.1 Timer Write Control during Count Operation). * Measurement period select The TEDGSEL bit in the TRAIOC register selects the measurement period of the input pulse. * Measured pulse input pin select function P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register. * Digital filter function Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital filter and select the sampling frequency.
Select functions
NOTE: 1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a longer "H" and "L" width than the timer RA prescaler period. If a pulse with a shorter period is input to the TRAIO pin, the input may be ignored.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 146 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RA I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TRAIOC Bit Symbol
Address 0101h Bit Name TRAIO polarity sw itch bit
TEDGSEL
After Reset 00h Function 0 : Measures measurement pulse from one rising edge to next rising edge 1 : Measures measurement pulse from one falling edge to next falling edge Set to 0 in pulse period measurement mode.
RW
RW
TOPCR TOENA TIOSEL
TRAIO output control bit TRAO output enable bit
_____
RW RW
_____
INT1/TRAIO select bit TRAIO input filter select bits (1)
0 : INT1/TRAIO pin (P1_7) _____ 1 : INT1/TRAIO pin (P1_5)
b5 b4
RW
TIPF0
TIPF1 -- (b7-b6)
0 0 : No filter 0 1 : Filter w ith f1 sampling 1 0 : Filter w ith f8 sampling 1 1 : Filter w ith f32 sampling
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
--
NOTE: 1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
Figure 14.10
TRAIOC Register in Pulse Period Measurement Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 147 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Underflow signal of timer RA prescaler
Set to 1 by program
TSTART bit in TRACR register
1 0
Starts counting
Measurement pulse (TRAIO pin input)
1 0
TRA reloads TRA reloads
Contents of TRA
0Fh 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh
01h 00h 0Fh 0Eh
Underflow
Retained
Retained
Contents of read-out buffer(1)
0Fh
0Eh
0Dh
0Bh 0Ah
09h
0Dh
01h 00h 0Fh 0Eh
TRA read(3) (Note 2) (Note 2)
TEDGF bit in TRACR register
1 0
Set to 0 by program (Note 4) (Note 6)
TUNDF bit in TRACR register
1 0
Set to 0 by program (Note 5)
IR bit in TRAIC register
1 0
Set to 0 when interrupt request is acknowledged, or set by program
Conditions: The period from one rising edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with the default value of the TRA register as 0Fh.
NOTES: 1. The contents of the read-out buffer can be read by reading the TRA register in pulse period measurement mode. 2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer RA prescaler underflows for the second time. 3. The TRA register should be read before the next active edge is input after the TEDGF bit is set to 1 (active edge found). The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next active edge is input, the measured result of the previous period is retained. 4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the TUNDF bit in the TRACR register. 5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit. 6. Bits TUNDF and TEDGF are both set to 1 if timer RA underflows and reloads on an active edge simultaneously.
Figure 14.11
Operating Example of Pulse Period Measurement Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 148 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.1.6
Notes on Timer RA
* Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the count starts. * Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. * In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction. * When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts. * The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts. * When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0. * The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA. * When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source clock for each write interval. * When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 149 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.2
Timer RB
Timer RB is an 8-bit timer with an 8-bit prescaler. The prescaler and timer each consist of a reload register and counter (refer to Tables 14.7 to 14.10 the Specifications of Each Mode). Timer RB has timer RB primary and timer RB secondary as reload registers. The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting and reloading. Figure 14.12 shows a Block Diagram of Timer RB. Figures 14.13 to 14.15 show the registers associated with timer RB. Timer RB has four operation modes listed as follows: * Timer mode: * Programmable waveform generation mode: * Programmable one-shot generation mode: * Programmable wait one-shot generation mode:
The timer counts an internal count source (peripheral function clock or timer RA underflows). The timer outputs pulses of a given width successively. The timer outputs a one-shot pulse. The timer outputs a delayed one-shot pulse.
Data bus TRBSC register Reload register TRBPR register Reload register Timer RB interrupt
Reload register TCK1 to TCK0 bits f1 f8
Timer RA underflow = 00b = 01b = 10b = 11b
TCKCUT bit Counter TRBPRE register (prescaler) TSTART bit TOSSTF bit INT0 interrupt
Input polarity selected to be one edge or both edges
Counter (timer RB) (Timer) TMOD1 to TMOD0 bits = 10b or 11b
f2
INT0 pin
Digital filter
Polarity select INOSEG bit TOPL = 1
Q Toggle flip-flop CK Q CLR
INT0PL bit TMOD1 to TMOD0 bits = 01b, 10b, 11b TOCNT = 0 TRBO pin P3_1 bit in P3 register TOCNT = 1 TSTART, TCSTF: Bit in TRBCR register TOSSTF: Bit in TRBOCR register TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register INT0EN bit
INOSTG bit
TOPL = 0
TCSTF bit TMOD1 to TMOD0 bits = 01b, 10b, 11b
Figure 14.12
Block Diagram of Timer RB
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 150 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RB Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRBCR Bit Symbol TSTART TCSTF TSTOP -- (b7-b3)
Address 0108h Bit Name Timer RB count start bit(1)
After Reset 00h Function 0 : Count stops 1 : Count starts
RW RW RO RW --
Timer RB count status flag(1) 0 : Count stops 1 : During count(3) Timer RB count forcible stop When this bit is set to 1, the count is forcibly bit(1, 2) stopped. When read, its content is 0. Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NOTES: 1. Refer to 14.2.5 Notes on Tim er RB. 2. When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit in the TRBOCR register are set to values after a reset. 3. Indicates that count operation is in progress in timer mode or programmable w aveform mode. In programmable oneshot generation mode or programmable w ait one-shot generation mode, indicates that a one-shot pulse trigger has been acknow ledged.
Timer RB One-Shot Control Register(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRBOCR Bit Symbol TOSST
Address 0109h Bit Name Timer RB one-shot start bit Timer RB one-shot stop bit
After Reset 00h Function When this bit is set to 1, one-shot trigger generated. When read, its content is 0. When this bit is set to 1, counting of one-shot pulses (including programmable w ait one-shot pulses) stops. When read, its content is 0. 0 : One-shot stopped 1 : One-shot operating (Including w ait period)
RW RW
TOSSP Timer RB one-shot status flag(1)
RW
TOSSTF -- (b7-b3)
RO --
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NOTES: 1. When 1 is set to the TSTOP bit in the TRBCR register, the TOSSTF bit is set to 0. 2. This register is enabled w hen bits TMOD1 to TMOD0 in the TRBMR register is set to 10b (programmable one-shot generation mode) or 11b (programmable w ait one-shot generation mode).
Figure 14.13
Registers TRBCR and TRBOCR
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 151 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG -- (b7-b4)
Address After Reset 010Ah 00h Bit Name Function Timer RB output level select Function varies depending on operating mode. bit Timer RB output sw itch bit One-shot trigger control bit One-shot trigger polarity select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0.
RW RW RW RW RW --
Timer RB Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRBMR Bit Symbol TMOD0
Address 010Bh Bit Name Timer RB operating mode select bits (1)
After Reset 00h Function
b1 b0
RW RW
TMOD1 -- (b2) TWRC
0 0 : Timer mode 0 1 : Programmable w aveform generation mode 1 0 : Programmable one-shot generation mode 1 1 : Programmable w ait one-shot generation mode
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RB w rite control bit(2) Timer RB count source select bits (1) 0 : Write to reload register and counter 1 : Write to reload register only
b5 b4
-- RW
TCK0
TCK1 -- (b6) TCKCUT
0 0 : f1 0 1 : f8 1 0 : Timer RA underflow 1 1 : f2
RW
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RB count source cutoff bit(1) 0 : Provides count source 1 : Cuts off count source
-- RW
NOTES: 1. Change bits TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bits in the TRBCR register set to 0 (count stops). 2. The TWRC bit can be set to either 0 or 1 in timer mode. In programmable w aveform generation mode, programmable one-shot generation mode, or programmable w ait one-shot generation mode, the TWRC bit must be set to 1 (w rite to reload register only).
Figure 14.14
Registers TRBIOC and TRBMR
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 152 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RB Prescaler Register(1)
b7 b0
Symbol TRBPRE Mode Timer mode Programmable w aveform generation mode Programmable one-shot generation mode
Address 010Ch Function Counts an internal count source or timer RA underflow s Counts an internal count source or timer RA underflow s Counts an internal count source or timer RA underflow s
After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh
RW RW RW RW RW
Programmable w ait one-shot Counts an internal count source or timer RA generation mode underflow s NOTE: 1. When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.
Timer RB Secondary Register(3, 4)
b7 b0
Symbol TRBSC Mode Timer mode Programmable w aveform generation mode Programmable one-shot generation mode Disabled
Address 010Dh Function
After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh
RW -- WO(2) -- WO(2)
Counts timer RB prescaler underflow s (1) Disabled
Programmable w ait one-shot Counts timer RB prescaler underflow s generation mode (one-shot w idth is counted)
NOTES: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. 2. The count value can be read out by reading the TRBPR register even w hen the secondary period is being counted. 3. When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh. 4. To w rite to the TRBSC register, perform the follow ing steps. (1) Write the value to the TRBSC register. (2) Write the value to the TRBPR register. (If the value does not change, w rite the same value second time.)
Timer RB Primary Register(2)
b7 b0
Symbol TRBPR Mode Timer mode Programmable w aveform generation mode Programmable one-shot generation mode
Address 010Eh Function Counts timer RB prescaler underflow s Counts timer RB prescaler underflow s (1) Counts timer RB prescaler underflow s (one-shot w idth is counted)
After Reset FFh Setting Range 00h to FFh 00h to FFh 00h to FFh 00h to FFh
RW RW RW RW RW
Programmable w ait one-shot Counts timer RB prescaler underflow s generation mode (w ait period w idth is counted) NOTES: 1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted. 2. When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
Figure 14.15
Registers TRBPRE, TRBSC, and TRBPR Page 153 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
14. Timers
14.2.1
Timer Mode
In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table 14.7 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode. Figure 14.16 shows the TRBIOC Register in Timer Mode. Table 14.7 Timer Mode Specifications Specification f1, f2, f8, timer RA underflow * Decrement * When the timer underflows, it reloads the reload register contents before the count continues (when timer RB underflows, the contents of timer RB primary reload register is reloaded). 1/(n+1)(m+1) n: setting value in TRBPRE register, m: setting value in TRBPR register 1 (count starts) is written to the TSTART bit in the TRBCR register. * 0 (count stops) is written to the TSTART bit in the TRBCR register. * 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. When timer RB underflows [timer RB interrupt]. Programmable I/O port Programmable I/O port or INT0 interrupt input The count value can be read out by reading registers TRBPR and TRBPRE. * When registers TRBPRE and TRBPR are written while the count is stopped, values are written to both the reload register and counter. * When registers TRBPRE and TRBPR are written to while count operation is in progress: If the TWRC bit in the TRBMR register is set to 0, the value is written to both the reload register and the counter. If the TWRC bit is set to 1, the value is written to the reload register only. (Refer to 14.2.1.1 Timer Write Control during Count Operation.)
Item Count sources Count operations
Divide ratio Count start condition Count stop conditions Interrupt request generation timing TRBO pin function INT0 pin function Read from timer Write to timer
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol TRBIOC Bit Symbol TOPL TOCNT INOSTG INOSEG -- (b7-b4)
Address After Reset 010Ah 00h Bit Name Function Timer RB output level select Set to 0 in timer mode. bit Timer RB output sw itch bit One-shot trigger control bit One-shot trigger polarity select bit Nothing is assigned. If necessary, set to 0. When read, the content is 0.
RW RW RW RW RW --
Figure 14.16
TRBIOC Register in Timer Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 154 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.2.1.1
Timer Write Control during Count Operation
Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to select whether writing to the prescaler or timer during count operation is performed to both the reload register and counter or only to the reload register. However, values are transferred from the reload register to the counter of the prescaler in synchronization with the count source. In addition, values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be shifted if the prescaler value changes. Figure 14.17 shows an Operating Example of Timer RB when Counter Value is Rewritten during Count Operation.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 155 of 485
R8C/24 Group, R8C/25 Group
14. Timers
When the TWRC bit is set to 0 (write to reload register and counter)
Set 01h to the TRBPRE register and 25h to the TRBPR register by a program.
Count source
After writing, the reload register is written with the first count source.
Reloads register of timer RB prescaler
Previous value
Reload with the second count source Reload on underflow
New value (01h)
Counter of timer RB prescaler
06h
05h
04h
01h
00h
01h
00h
01h
00h
01h
00h
After writing, the reload register is written on the first underflow.
Reloads register of timer RB
Previous value
New value (25h)
Reload on the second underflow
Counter of timer RB
03h
02h
25h
24h
IR bit in TRBIC register
0
The IR bit remains unchanged until underflow is generated by a new value.
When the TWRC bit is set to 1 (write to reload register only)
Set 01h to the TRBPRE register and 25h to the TRBPR register by a program.
Count source
After writing, the reload register is written with the first count source.
Reloads register of timer RB prescaler
Previous value
New value (01h)
Reload on underflow
Counter of timer RB prescaler
06h
05h
04h
03h
02h
01h
00h
01h
00h
01h
00h
01h
00h
01h
After writing, the reload register is written on the first underflow.
Reloads register of timer RB
Previous value
New value (25h)
Reload on underflow
Counter of timer RB
03h
02h
01h
00h
25h
IR bit in TRBIC register
0
Only the prescaler values are updated, extending the duration until timer RB underflow.
The above applies under the following conditions. Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).
Figure 14.17
Operating Example of Timer RB when Counter Value is Rewritten during Count Operation Page 156 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
14. Timers
14.2.2
Programmable Waveform Generation Mode
In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table 14.8 Programmable Waveform Generation Mode Specifications). Counting starts by counting the setting value in the TRBPR register. The TRBOCR register is unused in this mode. Figure 14.18 shows the TRBIOC Register in Programmable Waveform Generation Mode. Figure 14.19 shows an Operating Example of Timer RB in Programmable Waveform Generation Mode. Table 14.8 Programmable Waveform Generation Mode Specifications Specification
f1, f2, f8, timer RA underflow * Decrement * When the timer underflows, it reloads the contents of the primary reload and secondary reload registers alternately before the count continues. Width and period of Primary period: (n+1)(m+1)/fi output waveform Secondary period: (n+1)(p+1)/fi Period: (n+1){(m+1)+(p+1)}/fi fi: Count source frequency n: Value set in TRBPRE register m: Value set in TRBPR register p: Value set in TRBSC register Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register. Count stop conditions * 0 (count stops) is written to the TSTART bit in the TRBCR register. * 1 (count forcibly stops) is written to the TSTOP bit in the TRBCR register. Interrupt request In half a cycle of the count source, after timer RB underflows during the generation timing secondary period (at the same time as the TRBO output change) [timer RB interrupt] TRBO pin function Programmable output port or pulse output INT0 pin function Read from timer Write to timer Programmable I/O port or INT0 interrupt input The count value can be read out by reading registers TRBPR and TRBPRE(1). * When registers TRBPRE, TRBSC, and TRBPR are written while the count is stopped, values are written to both the reload register and counter. * When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only.(2) * Output level select function The TOPL bit in the TRBIOC register selects the output level during primary and secondary periods. * TRBO pin output switch function Timer RB pulse output or P3_1 latch output is selected by the TOCNT bit in the TRBIOC register.(3)
Item Count sources Count operations
Select functions
NOTES: 1. Even when counting the secondary period, the TRBPR register may be read. 2. The set values are reflected in the waveform output beginning with the following primary period after writing to the TRBPR register. 3. The value written to the TOCNT bit is enabled by the following. * When count starts. * When a timer RB interrupt request is generated. The contents after the TOCNT bit is changed are reflected from the output of the following primary period.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 157 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TRBIOC Bit Symbol
TOPL
Address 010Ah Bit Name Timer RB output level select 0 : Outputs bit Outputs Outputs 1 : Outputs Outputs Outputs Timer RB output sw itch bit One-shot trigger control bit One-shot trigger polarity select bit
After Reset 00h Function "H" for primary period "L" for secondary period "L" w hen the timer is stopped "L" for primary period "H" for secondary period "H" w hen the timer is stopped
RW
RW
TOCNT INOSTG INOSEG -- (b7-b4)
0 : Outputs timer RB w aveform 1 : Outputs value in P3_1 port latch Set to 0 in programmable w aveform generation mode.
RW RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Figure 14.18
TRBIOC Register in Programmable Waveform Generation Mode
Set to 1 by program
TSTART bit in TRBCR register
1 0
Count source
Timer RB prescaler underflow signal
Timer RB secondary reloads
Timer RB primary reloads
Counter of timer RB
01h
00h
02h
01h
00h
01h
00h
02h
Set to 0 when interrupt request is acknowledged, or set by program.
IR bit in TRBIC register
1 0
Set to 0 by program
TOPL bit in TRBIO register
1 0
Waveform output starts Waveform output inverted Waveform output starts
1 TRBO pin output 0
Primary period Secondary period Primary period
Initial output is the same level as during secondary period.
The above applies under the following conditions. TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)
Figure 14.19
Operating Example of Timer RB in Programmable Waveform Generation Mode Page 158 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
14. Timers
14.2.3
Programmable One-shot Generation Mode
In programmable one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 14.9 Programmable One-Shot Generation Mode Specifications). When a trigger is generated, the timer starts operating from the point only once for a given period equal to the set value in the TRBPR register. The TRBSC register is not used in this mode. Figure 14.20 shows the TRBIOC Register in Programmable One-Shot Generation Mode. Figure 14.21 shows an Operating Example of Programmable One-Shot Generation Mode. Table 14.9 Programmable One-Shot Generation Mode Specifications Specification
f1, f2, f8, timer RA underflow * Decrement the setting value in the TRBPR register * When the timer underflows, it reloads the contents of the reload register before the count completes and the TOSSTF bit is set to 0 (one-shot stops). * When the count stops, the timer reloads the contents of the reload register before it stops. One-shot pulse (n+1)(m+1)/fi output time fi: Count source frequency, n: Setting value in TRBPRE register, m: Setting value in TRBPR register(2) Count start conditions * The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated. * Set the TOSST bit in the TRBOCR register to 1 (one-shot starts) * Input trigger to the INT0 pin Count stop conditions * When reloading completes after timer RB underflows during primary period. * When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops). * When the TSTART bit in the TRBCR register is set to 0 (count stops). * When the TSTOP bit in the TRBCR register is set to 1 (count forcibly stops). Interrupt request In half a cycle of the count source, after the timer underflows (at the same time as generation timing the TRBO output ends) [timer RB interrupt] TRBO pin function Pulse output INT0 pin functions * When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input * When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) The count value can be read out by reading registers TRBPR and TRBPRE. * When registers TRBPRE and TRBPR are written while the count is stopped, values are written to both the reload register and counter. * When registers TRBPRE and TRBPR are written during the count, values are written to the reload register only (the data is transferred to the counter at the following reload).(1) * Output level select function The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse waveform. * One-shot trigger select function Refer to 14.2.3.1 One-Shot Trigger Selection.
Item Count sources Count operations
Read from timer Write to timer
Select functions
NOTES: 1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register. 2. Do not set both the TRBPRE and TRBPR registers to 00h.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 159 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TRBIOC Bit Symbol
TOPL
Address 010Ah Bit Name Timer RB Output Level Select Bit
0 : Outputs Outputs 1 : Outputs Outputs
After Reset 00h Function one-shot pulse "H" "L" w hen the timer is stopped one-shot pulse "L" "H" w hen the timer is stopped
RW
RW
TOCNT INOSTG INOSEG -- (b7-b4)
Timer RB Output Sw itch Bit One-Shot Trigger Control Bit(1) One-Shot Trigger Polarity Select Bit(1)
Set to 0 in programmable one-shot generation mode.
_____
RW RW RW --
0 : INT0 pin one-shot trigger disabled _____ 1 : INT0 pin one-shot trigger enabled 0 : Falling edge trigger 1 : Rising edge trigger
Nothing is assigned. If necessary, set to 0. When read, its content is 0.
NOTE: 1. Refer to 14.2.3.1 One-shot Trigger Selection.
Figure 14.20
TRBIOC Register in Programmable One-Shot Generation Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 160 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Set to 1 by program
TSTART bit in TRBCR register
1 0
Set to 1 by setting 1 to TOSST bit in TRBOCR register Set to 0 when counting ends Set to 1 by INT0 pin input trigger
TOSSTF bit in TRBOCR register
1 0
INT0 pin input
Count source
Timer RB prescaler underflow signal
Count starts Timer RB primary reloads Count starts Timer RB primary reloads
Counter of timer RB
01h
00h
01h
00h
01h
Set to 0 when interrupt request is acknowledged, or set by program.
IR bit in TRBIC register
1 0
Set to 0 by program
TOPL bit in TRBIOC register
1 0
Waveform output starts Waveform output ends Waveform output starts Waveform output ends
1 TRBIO pin output 0
The above applies under the following conditions. TRBPRE = 01h, TRBPR = 01h TRBIOC register TOPL = 0, TOCNT = 0 INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge)
Figure 14.21
Operating Example of Programmable One-Shot Generation Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 161 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.2.3.1
One-Shot Trigger Selection
In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts). A one-shot trigger can be generated by either of the following causes: * 1 is written to the TOSST bit in the TRBOCR register by a program. * Trigger input from the INT0 pin. When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot generation mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation mode, count operation starts for the wait period.) If a one-shot trigger occurs while the TOSSTF bit is set to 1, no retriggering occurs. To use trigger input from the INT0 pin, input the trigger after making the following settings: * Set the PD4_5 bit in the PD4 register to 0 (input port). * Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register. * Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select falling or rising edge with the INOSEG bit in TRBIOC register. * Set the INT0EN bit in the INTEN register to 0 (enabled). * After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger enabled). Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin. * Processing to handle the interrupts is required. Refer to 12. Interrupts, for details. * If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The INOSEG bit in the TRBIOC register does not affect INT0 interrupts). * If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the value of the IR bit in the INT0IC register changes.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 162 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.2.4
Programmable Wait One-Shot Generation Mode
In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program or an external trigger input (input to the INT0 pin) (refer to Table 14.10 Programmable Wait One-Shot Generation Mode Specifications). When a trigger is generated from that point, the timer outputs a pulse only once for a given length of time equal to the setting value in the TRBSC register after waiting for a given length of time equal to the setting value in the TRBPR register. Figure 14.22 shows the TRBIOC Register in Programmable Wait One-Shot Generation Mode. Figure 14.23 shows an Operating Example of Programmable Wait One-Shot Generation Mode.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 163 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.10
Programmable Wait One-Shot Generation Mode Specifications
Specification f1, f2, f8, timer RA underflow * Decrement the timer RB primary setting value. * When a count of the timer RB primary underflows, the timer reloads the contents of timer RB secondary before the count continues. * When a count of the timer RB secondary underflows, the timer reloads the contents of timer RB primary before the count completes and the TOSSTF bit is set to 0 (one-shot stops). * When the count stops, the timer reloads the contents of the reload register before it stops. Wait time (n+1)(m+1)/fi fi: Count source frequency n: Value set in the TRBPRE register, m Value set in the TRBPR register(2) One-shot pulse output time (n+1)(p+1)/fi fi: Count source frequency n: Value set in the TRBPRE register, p: Value set in the TRBSC register Count start conditions * The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger is generated. * Set the TOSST bit in the TRBOCR register to 1 (one-shot starts). * Input trigger to the INT0 pin Count stop conditions * When reloading completes after timer RB underflows during secondary period. * When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops). * When the TSTART bit in the TRBCR register is set to 0 (count starts). * When the TSTOP bit in the TRBCR register is set to 1 (count forcibly stops). Interrupt request In half a cycle of the count source after timer RB underflows during generation timing secondary period (complete at the same time as waveform output from the TRBO pin) [timer RB interrupt]. TRBO pin function Pulse output INT0 pin functions * When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger disabled): programmable I/O port or INT0 interrupt input * When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigger enabled): external trigger (INT0 interrupt input) The count value can be read out by reading registers TRBPR and TRBPRE. * When registers TRBPRE, TRBSC, and TRBPR are written while the count stops, values are written to both the reload register and counter. * When registers TRBPRE, TRBSC, and TRBPR are written to during count operation, values are written to the reload registers only.(1) * Output level select function The TOPL bit in the TRBIOC register selects the output level of the oneshot pulse waveform. * One-shot trigger select function Refer to 14.2.3.1 One-Shot Trigger Selection.
Item Count sources Count operations
Read from timer Write to timer
Select functions
NOTES: 1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR. 2. Do not set both the TRBPRE and TRBPR registers to 00h.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 164 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RB I/O Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TRBIOC Bit Symbol
TOPL
Address 010Ah Bit Name Timer RB output level select 0 : Outputs bit Outputs w ait. 1 : Outputs Outputs w ait. Timer RB output sw itch bit
After Reset 00h Function one-shot pulse "H". "L" w hen the timer stops or during one-shot pulse "L". "H" w hen the timer stops or during
RW
RW
TOCNT INOSTG INOSEG -- (b7-b4)
Set to 0 in programmable w ait one-shot generation mode.
_____
RW RW RW --
One-shot trigger control bit(1) 0 : INT0 pin one-shot trigger disabled _____ 1 : INT0 pin one-shot trigger enabled One-shot trigger polarity 0 : Falling edge trigger select bit(1) 1 : Rising edge trigger Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NOTE: 1. Refer to 14.2.3.1 One-shot Trigger Selection.
Figure 14.22
TRBIOC Register in Programmable Wait One-Shot Generation Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 165 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Set to 1 by program
TSTART bit in TRBCR register
1 0
Set to 1 by setting 1 to TOSST bit in TRBOCR register, or INT0 pin input trigger. Set to 0 when counting ends
TOSSTF bit in TRBOCR register
1 0
INT0 pin input
Count source
Timer RB prescaler underflow signal
Count starts Timer RB secondary reloads Timer RB primary reloads
Counter of timer RB
01h
00h
04h
03h
02h
01h
00h
01h
Set to 0 when interrupt request is acknowledged, or set by program.
IR bit in TRBIC register
1 0
Set to 0 by program
TOPL bit in TRBIOC register
1 0
Wait starts Waveform output starts Waveform output ends
1 TRBIO pin output 0
Wait (primary period) One-shot pulse (secondary period)
The above applies under the following conditions. TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h INOSTG = 1 (INT0 one-shot trigger enabled) INOSEG = 1 (edge trigger at rising edge)
Figure 14.23
Operating Example of Programmable Wait One-Shot Generation Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 166 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.2.5
Notes on Timer RB
* Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the count starts. * Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. * In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR register to 1 (one-shot stops), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops. * The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR. * If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately. * If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.
14.2.5.1
Timer mode
The following workaround should be performed in timer mode. To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: * When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. * When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 167 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.2.5.2
Programmable waveform generation mode
The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: * When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. * When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period A shown in Figures 14.24 and 14.25. The following shows the detailed workaround examples. * Workaround example (a): As shown in Figure 14.24, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These write operations must be completed by the beginning of period A.
Period A
Count source/ prescaler underflow signal
TRBO pin output
Primary period
Secondary period
IR bit in TRBIC register
(a)
Interrupt request is acknowledged (b)
Ensure sufficient time
Interrupt request is generated
Instruction in Interrupt sequence interrupt routine
Set the secondary and then the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 14.24
Workaround Example (a) When Timer RB interrupt is Used
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 168 of 485
R8C/24 Group, R8C/25 Group
14. Timers
* Workaround example (b): As shown in Figure 14.25 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A. If the port register's bit value is read after the port direction register's bit corresponding to the TRBO pin is set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/ prescaler underflow signal
TRBO pin output
Read value of the port register's bit corresponding to the TRBO pin (when the bit in the port direction register is set to 0)
Primary period
Secondary period
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion is detected at the end of the secondary period.
Upon detecting (i), set the secondary and then the primary register immediately.
Figure 14.25
Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case, registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
14.2.5.3
Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: * When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval. * When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 169 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.2.5.4
Programmable wait one-shot generation mode
The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: * When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. * When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. (3) Set registers TRBSC and TRBPR using the following procedure. (a) To use "INT0 pin one-shot trigger enabled" as the count start condition Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before trigger input from the INT0 pin. (b) To use "writing 1 to TOSST bit" as the start condition Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the TOSST bit.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 170 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3
Timer RD
Timer RD has 2 16-bit timers (channels 0 and 1). Each channel has 4 I/O pins. The operation clock of timer RD is f1 or fOCO40M. Table 14.11 lists the Timer RD Operation Clocks. Table 14.11 Timer RD Operation Clocks
Condition Operation Clock of Timer RD The count source is f1, f2, f4, f8, f32, or TRDCLK input f1 (bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to a value from 000b to 101b). The count source is fOCO40M fOCO40M (bits TCK2 to TCK0 in registers TRDCR0 and TRDCR1 are set to 110b).
Figure 14.26 shows a Block Diagram of Timer RD. Timer RD has 5 modes: * Timer mode - Input capture function Transfer the counter value to a register with an external signal as the trigger - Output compare function Detect register value matches with a counter (Pin output can be changed at detection) The following 4 modes use the output compare function. * PWM mode Output pulse of any width continuously * Reset synchronous PWM mode Output three-phase waveforms (6) without sawtooth wave modulation and dead time * Complementary PWM mode Output three-phase waveforms (6) with triangular wave modulation and dead time * PWM3 mode Output PWM waveforms (2) with a fixed period In the input capture function, output compare function, and PWM mode, channels 0 and 1 have the equivalent functions, and functions or modes can be selected individually for each pin. Also, a combination of these functions and modes can be used in 1 channel. In reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, a waveform is output with a combination of counters and registers in channels 0 and 1. Tables 14.12 to 14.20 list the Pin Functions of timer RD.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 171 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.12
Bit EA0 0 0 Setting value X
Pin Functions TRDIOA0/TRDCLK(P2_0)
TRDFCR TRDIORA0 PWM3 STCLK CMD1, CMD0 IOA3 IOA2_IOA0 0 1 1 1 0 0 0 1 00b 00b 00b XXb X 1 X X XXXb Function PWM3 mode waveform output
Register TRDOER1
001b, 01Xb Timer mode waveform output (output compare function) 1XXb 000b
Timer mode trigger input (input capture function)(1)
External clock input (TRDCLK)(1) I/O port
Other than above
X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_0 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function) and external clock input (TRDCLK).
Table 14.13
Bit
Pin Functions TRDIOB0(P2_1)
TRDFCR PWM3 CMD1, CMD0 X X 0 1 1 1
1Xb
Register TRDOER1 EB0 0 0 0 Setting value 0 0 X
TRDPMR PWMB0 X X X 1 0 0
TRDIORA0 IOB2_IOB0 XXXb XXXb XXXb XXXb
001b, 01Xb
Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM3 mode waveform output PWM mode waveform output Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
01b 00b 00b 00b 00b Other than above
1XXb
I/O port
X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_1 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.14
Register Bit
Pin Functions TRDIOC0(P2_2)
TRDFCR PWM3 CMD1, CMD0 X X 1 1 1
1Xb
TRDOER1
TRDPMR PWMC0 X X 1 0 0
TRDIORC0 IOC2_IOC0
EC0 0 0
Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
XXXb XXXb XXXb
001b, 01Xb
01b 00b 00b 00b Other than above
Setting value
0 0 X
1XXb
I/O port
X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_2 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 172 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.15
Register Bit
Pin Functions TRDIOD0(P2_3)
TRDFCR PWM3 CMD1, CMD0 X X 1 1 1
1Xb
TRDOER1
TRDPMR PWMD0 X X 1 0 0
TRDIORC0 IOD2_IOD0
ED0 0 0
Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
XXXb XXXb XXXb
001b, 01Xb
01b 00b 00b 00b Other than above
Setting value
0 0 X
1XXb
I/O port
X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_3 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.16
Register Bit
Pin Functions TRDIOA1(P2_4)
TRDFCR PWM3 CMD1, CMD0 X X 1 1
1Xb
TRDOER1 EA1 0 0
TRDIORA1 IOA2_IOA0 XXXb XXXb
001b, 01Xb
Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
01b 00b 00b
Setting value
0 X
1XXb
Other than above
I/O port
X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_4 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.17
Register Bit
Pin Functions TRDIOB1(P2_5)
TRDFCR PWM3 CMD1, CMD0 X X 1 1 1
1Xb
TRDOER1
TRDPMR PWMB1 X X 1 0 0
TRDIORA1 IOB2_IOB0
EB1 0 0
Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
XXXb XXXb XXXb
001b, 01Xb
01b 00b 00b 00b Other than above
Setting value
0 0 X
1XXb
I/O port
X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_5 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 173 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.18
Register Bit
Pin Functions TRDIOC1(P2_6)
TRDFCR PWM3 CMD1, CMD0 X X 1 1 1
1Xb
TRDOER1
TRDPMR PWMC1 X X 1 0 0
TRDIORC1 IOC2_IOC0
EC1 0 0
Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
XXXb XXXb XXXb
001b, 01Xb
01b 00b 00b 00b Other than above
Setting value
0 0 X
1XXb
I/O port
X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_6 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.19
Register Bit
Pin Functions TRDIOD1(P2_7)
TRDFCR PWM3 CMD1, CMD0 X X 1 1 1
1Xb
TRDOER1
TRDPMR PWMD1 X X 1 0 0
TRDIORC1 IOD2_IOD0
ED1 0 0
Function Complementary PWM mode waveform output Reset synchronous PWM mode waveform output PWM mode waveform output Timer mode waveform output (output compare function)
Timer mode trigger input (input capture function)(1)
XXXb XXXb XXXb
001b, 01Xb
01b 00b 00b 00b Other than above
Setting value
0 0 X
1XXb
I/O port
X: can be 0 or 1, no change in outcome NOTE: 1. Set the PD2_7 bit in the PD2 register to 0 (input mode) at timer mode trigger input (input capture function).
Table 14.20
Register Bit Setting value
Pin Functions INT0(P4_5)
INTEN INT0PL 0 INT0EN
1
TRDOER2 PTO 1
PD4 PD4_5 0
Function Pulse output forced cutoff signal input I/O port or INT0 interrupt input
Other than above
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 174 of 485
R8C/24 Group, R8C/25 Group
14. Timers
f1, f2, f4, f8, f32, fOCO40M
Channel i
TRDi register TRDGRAi register TRDGRBi register TRDGRCi register TRDGRDi register TRDDFi register TRDCRi register TRDIORAi register TRDIORCi register
Data bus
INT0 Count source select circuit TRDIOA0/TRDCLK TRDIOB0
Timer RD control circuit
TRDIOC0 TRDIOD0 TRDIOA1 TRDIOB1 TRDIOC1 TRDIOD1
TRDSRi register TRDIERi register TRDPOCRi register
TRDSTR register TRDMR register TRDPMR register TRDFCR register TRDOER1 register TRDOER2 register TRDOCR register
Channel 0 interrupt request Channel 1 interrupt request A/D trigger
i = 0 or 1
Figure 14.26
Block Diagram of Timer RD
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 175 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.1
Count Sources
The count source selection method is the same in all modes. However, in PWM3 mode, the external clock cannot be selected. Table 14.21 Count Source Selection Selection The count source is selected by bits TCK2 to TCK0 in the TRDCRi register. The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator frequency). Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M). The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (count source: external clock). The valid edge is selected by bits CKEG1 to CKEG0 in the TRDCRi register. The PD2_0 bit in the PD2 register is set to 0 (input mode).
Count Source f1, f2, f4, f8, f32 fOCO40M(1)
External signal input to TRDCLK pin
i = 0 or 1 NOTE: 1. The count source fOCO40M can be used with VCC = 3.0 to 5.5 V.
f1 f2 f4 f8 f32 fOCO40M
TCK2 to TCK0 = 000b = 001b = 010b = 011b = 100b = 110b = 101b STCLK = 1 CKEG1 to CKEG0 Valid edge selected Count source TRDi register
TRDCLK/ TRDIOA0 STCLK = 0
TRDIOA0 I/O or programmable I/O port
TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register STCLK: Bit in TRDFCR register
Figure 14.27
Block Diagram of Count Source
Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation clock of timer RD (refer to Table 14.11 Timer RD Operation Clocks). When selecting fOCO40M for the count source, set the FRA00 bit in the FRA0 register to 1 (high-speed onchip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi register (i = 0 or 1) to 110b (fOCO40M).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 176 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.2
Buffer Operation
The TRDGRCi (i = 0 or 1) register can be used as the buffer register of the TRDGRAi register, and the TRDGRDi register can be used as the buffer register of the TRDGRBi register by means of bits BFCi and BFDi in the TRDMR register. * TRDGRAi buffer register: TRDGRCi register * TRDGRBi buffer register: TRDGRDi register Buffer operation depends on the mode. Table 14.22 lists the Buffer Operation in Each Mode. Figure 14.28 shows the Buffer Operation in Input Capture Function, and Figure 14.29 shows the Buffer Operation in Output Compare Function. Table 14.22 Buffer Operation in Each Mode Transfer Timing Input capture signal input Compare match with TRDi register and TRDGRAi (TRDGRBi) register Compare match withTRD0 register and TRDGRA0 register * Compare match with TRD0 register and TRDGRA0 register * TRD1 register underflow Compare match with TRD0 register and TRDGRA0 register Transfer Register Transfer content in TRDGRAi (TRDGRBi) register to buffer register Transfer content in buffer register to TRDGRAi (TRDGRBi) register Transfer content in buffer register to TRDGRAi (TRDGRBi) register Transfer content in buffer register to registers TRDGRB0, TRDGRA1, and TRDGRB1 Transfer content in buffer register to registers TRDGRA0, TRDGRB0, TRDGRA1, and TRDGRB1
Function and Mode Input capture function Output compare function PWM mode Reset synchronous PWM mode Complementary PWM mode PWM3 mode
i = 0 or 1
TRDIOAi input (input capture signal) TRDGRCi register (buffer) TRDGRAi register TRDi
TRDIOAi input
TRDi register
n-1
n Transfer
n+1
TRDGRAi register
m Transfer
n
TRDGRCi register (buffer)
m
i = 0 or 1 The above applies under the following conditions: * The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register). * Bits IOA2 to IOA0 in the TRDIORAi register are set to 100b (input capture at the falling edge).
Figure 14.28
Buffer Operation in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 177 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Compare match signal
TRDGRCi register (buffer)
TRDGRAi register
Comparator
TRDi
TRDi register
m-1
m
m+1
TRDGRAi register
m Transfer
n
TRDGRCi register (buffer)
n
TRDIOAi output i = 0 or 1 The above applies under the following conditions: * BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register). * Bits IOA2 to IOA0 in the TRDIORAi register are set to 001b ("L" output by the compare match).
Figure 14.29
Buffer Operation in Output Compare Function
Perform the following for the timer mode (input capture and output compare functions). When using the TRDGRCi (i = 0 or 1) register as the buffer register of the TRDGRAi register * Set the IOC3 bit in the TRDIORCi register to 1 (general register or buffer register). * Set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. When using the TRDGRDi register as the buffer register of the TRDGRBi register * Set the IOD3 bit in the TRDIORDi register to 1 (general register or buffer register). * Set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. Bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when also using registers TRDGRCi and TRDGRDi as the buffer register in the input capture function. When also using registers TRDGRCi and TRDGRDi as buffer registers for the output compare function, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, bits IMFC and IMFD in the TRDSRi register are set to 1 by a compare match with the TRDi register.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 178 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.3
Synchronous Operation
The TRD1 register is synchronized with the TRD0 register. * Synchronous preset When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the TRD0 and TRD1 registers after writing to the TRDi register. * Synchronous clear When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are set to 011b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register is set to 0000h. Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are set to 011b (synchronous clear), the TRD1 register is set to 0000h at the same time as the TRD0 register is set to 0000h.
TRDIOA0 input Set to 0000h by input capture Value in TRD0 register n writing
n
n is set
Value in TRD1 register
n
n is set
Set to 0000h with TRD0 register The above applies under the following conditions: * The SYNC bit in the TRDMR register is set to 1 (synchronous operation). * Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture). Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (set the TRD1 register to 0000h synchronizing with the TRD0 register). * Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b. * Bits CMD1 to CMD0 in the TRDFCR register are set to 00b. (Input capture at the rising edge of the TRDIOA0 input) The PWM 3 bit in the TRDFCR register is set to 1.
Figure 14.30
Synchronous Operation
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 179 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.4
Pulse Output Forced Cutoff
In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode, and PWM3 mode, the TRDIOji (i = 0 or 1, j = either A, B, C, or D) output pin can be forcibly set to a programmable I/O port by the INT0 pin input, and pulse output can be cut off. The pins used for output in these functions or modes can function as the output pin of timer RD when the applicable bit in the TRDOER1 register is set to 0 (enable timer RD output). When the PTO bit in the TRDOER2 register to 1 (INT0 of pulse output forced cutoff signal input enabled), all bits in the TRDOER1 register are set to 1 (disable timer RD output, the TRDIOji output pin is used as the programmable I/O port) after "L" is applied to the INT0 pin. The TRDIOji output pin is set to the programmable I/O port after "L" is applied to the INT0 pin and waiting for 1 to 2 cycles of the timer RD operation clock (refer to Table 14.11 Timer RD Operation Clocks). Set as below when using this function: * Set the pin status (high impedance, "L" or "H" output) to pulse output forced cutoff by registers P2 and PD2. * Set the INT0EN bit in the INTEN register to 1 (enable INT0 input) and the INT0PL bit to 0 (one edge). * Set the PD4_5 bit in the PD4 register to 0 (input mode). * Set the INT0 digital filter by bits INT0F1 to INT0F0 in the INTF register. * Set the PTO bit in the TRDOER2 register to 1 (enable pulse output forced cutoff signal input INT0). According to the selection of the POL bit in the INT0IC register and change of the INT0 pin input, the IR bit in the INT0IC register is set to 1 (interrupt request). Refer to 12. Interrupts for details of interrupts.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 180 of 485
R8C/24 Group, R8C/25 Group
14. Timers
EA0 bit writing value
EA0 bit DQ S Timer RD output data Port P2_0 output data Port P2_0 input data
INT0 input
PTO bit
TRDIOA0
EB0 bit writing value
EB0 bit DQ S Timer RD output data Port P2_1 output data Port P2_1 input data
TRDIOB0
EC0 bit writing value
EC0 bit DQ S Timer RD output data Port P2_2 output data Port P2_2 input data
TRDIOC0
ED0 bit writing value
ED0 bit DQ S Timer RD output data Port P2_3 output data Port P2_3 input data
TRDIOD0
EA1 bit writing value
EA1 bit DQ S Timer RD output data Port P2_4 output data Port P2_4 input data
TRDIOA1
EB1 bit writing value
EB1 bit DQ S Timer RD output data Port P2_5 output data Port P2_5 input data
TRDIOB1
EC1 bit writing value
EC1 bit DQ S Timer RD output data Port P2_6 output data Port P2_6 input data
TRDIOC1
ED1 bit writing value
ED1 bit DQ S Timer RD output data Port P2_7 output data Port P2_7 input data
TRDIOD1
PTO: Bit in TRDOER2 register EA0, EB0, EC0, ED0, EA1, EB1, EC1, ED1: Bits in TRDOER1 register
Figure 14.31
Pulse Output Forced Cutoff Page 181 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
14. Timers
14.3.5
Input Capture Function
The input capture function measures the external signal width and period. The content of the TRDi register (counter) is transferred to the TRDGRji register as a trigger of the TRDIOji (i = 0 or 1, j = either A, B, C, or D) pin external signal (input capture). Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, the input capture function, or any other mode or function, can be selected for each individual pin. The TRDGRA0 register can also select fOCO128 signal as input-capture trigger input. Figure 14.32 shows a Block Diagram of Input Capture Function, Table 14.23 lists the Input Capture Function Specifications. Figures 14.33 to 14.43 show the Registers Associated with Input Capture Function, and Figure 14.44 shows an Operating Example of Input Capture Function.
TRDIOAi(3)
Input capture signal
(Note 1)
TRDGRAi register
TRDi register
TRDGRCi register
TRDIOCi
Input capture signal Input capture signal
TRDIOBi
(Note 2)
TRDGRBi register
fOCO
Divided by 128
fOCO128
IOA3 = 0
Input capture signal
TRDIOA0
TRDGRDi register TRDIODi
IOA3 = 1
Input capture signal
NOTE 3: The trigger input of the TRDGRA0 register can select the TRDIOA0 pin input or fOCO128 signal.
i = 0 or 1 NOTE 1: When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register). NOTE 2: When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the buffer register of the TRDGRBi register).
Figure 14.32
Block Diagram of Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 182 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.23
Input Capture Function Specifications Specification f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Increment When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running operation). 1/fk x 65536 fk: Frequency of count source 1 (count starts) is written to the TSTARTi bit in the TRDSTR register. 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. * Input capture (valid edge of TRDIOji input or fOCO128 signal edge) * TRDi register overflows Programmable I/O port, input-capture input, or TRDCLK (external clock) input Programmable I/O port, or input-capture input (selectable by pin)
Item Count sources
Count operations Count period
Count start condition Count stop condition Interrupt request generation timing TRDIOA0 pin function TRDIOB0, TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 pin functions INT0 pin function Read from timer Write to timer
Select functions
Programmable I/O port or INT0 interrupt input The count value can be read by reading the TRDi register. * When the SYNC bit in the TRDMR register is set to 0 (channels 0 and 1 operate independently). Data can be written to the TRDi register. * When the SYNC bit in the TRDMR register is set to 1 (channels 0 and 1 operate synchronously). Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi register. * Input-capture input pin selected Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi. * Input-capture input valid edge selected The rising edge, falling edge, or both the rising and falling edges * The timing when the TRDi register is set to 0000h At overflow or input capture * Buffer operation (Refer to 14.3.2 Buffer Operation.) * Synchronous operation (Refer to 14.3.3 Synchronous Operation.) * Digital filter The TRDIOji input is sampled, and when the sampled input level match as 3 times, the level is determined. * Input-capture trigger selected fOCO128 can be selected for input-capture trigger input of the TRDGRA0 register.
i = 0 or 1, j = either A, B, C, or D
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 183 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol TRDSTR Bit Symbol TSTART0 TSTART1 CSEL0 CSEL1 -- (b7-b4)
Address 0137h Bit Name TRD0 count start flag TRD1 count start flag TRD0 count operation select bit TRD1 count operation select bit
After Reset 11111100b Function 0 : Count stops 1 : Count starts 0 : Count stops 1 : Count starts Set to 1 in the input capture function. Set to 1 in the input capture function.
RW RW RW RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
NOTE: 1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Register of Notes on Tim er RD.
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDMR Bit Symbol
Address 0138h Bit Name Timer RD synchronous bit
SYNC
After Reset 00001110b Function 0 : Registers TRD0 and TRD1 operate independently 1 : Registers TRD0 and TRD1 operate synchronously
RW
RW
-- (b3-b1) BFC0 BFD0 BFC1 BFD1
Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select 0 : General register bit 1 : Buffer register of TRDGRA0 register TRDGRD0 register function select 0 : General register bit 1 : Buffer register of TRDGRB0 register TRDGRC1 register function select 0 : General register bit 1 : Buffer register of TRDGRA1 register TRDGRD1 register function select 0 : General register bit 1 : Buffer register of TRDGRB1 register
-- RW RW RW RW
Figure 14.33
Registers TRDSTR and TRDMR in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 184 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD PWM Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
000
000
Symbol TRDPMR Bit Symbol PWMB0 PWMC0 PWMD0 -- (b3) PWMB1 PWMC1 PWMD1 -- (b7)
Address 0139h Bit Name PWM mode of TRDIOB0 select bit PWM mode of TRDIOC0 select bit PWM mode of TRDIOD0 select bit
After Reset 10001000b Function Set to 0 (timer mode) in the input capture function. Set to 0 (timer mode) in the input capture function. Set to 0 (timer mode) in the input capture function.
RW RW RW RW -- RW RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1. PWM mode of TRDIOB1 select bit PWM mode of TRDIOC1 select bit PWM mode of TRDIOD1 select bit Set to 0 (timer mode) in the input capture function. Set to 0 (timer mode) in the input capture function. Set to 0 (timer mode) in the input capture function.
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Figure 14.34
TRDPMR Register in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 185 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
1
00
Symbol TRDFCR Bit Symbol CMD0 CMD1
Address 013Ah Bit Name Combination mode select bits (1)
After Reset 10000000b Function Set to 00b (timer mode, PWM mode, or PWM3 mode) in the input capture function.
RW RW RW
OLS0
Normal-phase output level select bit This bit is disabled in the input capture (in reset synchronous PWM mode or function. complementary PWM mode) Counter-phase output level select bit This bit is disabled in the input capture (in reset synchronous PWM mode or function. complementary PWM mode) A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) External clock input select bit PWM3 mode select bit(2) This bit is disabled in the input capture function. This bit is disabled in the input capture function. 0 : External clock input disabled 1 : External clock input enabled Set this bit to 1 (other than PWM3 mode) in the input capture function.
RW
OLS1
RW
ADTRG
RW
ADEG
RW
STCLK PWM3
RW RW
NOTES: 1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled.
Figure 14.35
TRDFCR Register in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 186 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Digital Filter Function Select Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDDF0 TRDDF1 Bit Symbol DFA DFB DFC DFD -- (b5-b4)
Address 013Eh 013Fh Bit Name TRDIOA pin digital filter function select bit TRDIOB pin digital filter function select bit TRDIOC pin digital filter function select bit TRDIOD pin digital filter function select bit
After Reset 00h 00h Function 0 : Function is not used 1 : Function is used 0 : Function is not used 1 : Function is used 0 : Function is not used 1 : Function is used 0 : Function is not used 1 : Function is used RW RW RW RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Clock select bits for digital filter function
b7 b6
DFCK0
0 0 1 1
DFCK1
0 : f32 1 : f8 0 : f1 1 : Count source (clock selected by bits TCK2 to TCK0 in the TRDCRi register)
RW
RW
Figure 14.36
Registers TRDDF0 to TRDDF1 in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 187 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDCR0 TRDCR1 Bit Symbol TCK0
Address 0140h 0150h Bit Name Count source select bits
b2 b1 b0
After Reset 00h 00h Function 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : TRDCLK input(1) 0 : fOCO40M 1 : Do not set. RW RW
TCK1
RW
TCK2 External clock edge select bits (2) CKEG0
RW
b4 b3
CKEG1 TRDi counter clear select bits CCLR0
0 0 1 1
0 : Count at the rising edge 1 : Count at the falling edge 0 : Count at both edges 1 : Do not set.
RW
RW
b7 b6 b5
CCLR1
CCLR2
0 0 0 : Disable clear (free-running operation) 0 0 1 : Clear by input capture in the TRDGRAi register 0 1 0 : Clear by input capture in the TRDGRBi register 0 1 1 : Synchronous clear (clear simultaneously w ith other channel counter)(3) 1 0 0 : Do not set. 1 0 1 : Clear by input capture in the TRDGRCi register 1 1 0 : Clear by input capture in the TRDGRDi register 1 1 1 : Do not set.
RW
RW
RW
NOTES: 1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 3. This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate synchronously).
Figure 14.37
Registers TRDCR0 to TRDCR1 in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 188 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD I/O Control Register Ai (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol TRDIORA0 TRDIORA1 Bit Symbol
Address 0141h 0151h Bit Name TRDGRA control bits
b1 b0
After Reset 10001000b 10001000b Function 0 0 : Input capture to the TRDGRAi register at the rising edge 0 1 : Input capture to the TRDGRAi register at the falling edge 1 0 : Input capture to the TRDGRAi register at both edges 1 1 : Do not set. RW
IOA0
RW
IOA1
RW
IOA2 IOA3
TRDGRA mode select bit(1) Input capture input sw itch bit(3, 4) TRDGRB control bits
Set to 1 (input capture) in the input capture function. 0 : fOCO128 Signal 1 : TRDIOA0 pin input
b5 b4
RW RW
IOB0
IOB1
0 0 : Input capture to the TRDGRBi register at the rising edge 0 1 : Input capture to the TRDGRBi register at the falling edge 1 0 : Input capture to the TRDGRBi register at both edges 1 1 : Do not set. TRDGRB mode select bit(2) Set to 1 (input capture) in the input capture function.
RW
RW
IOB2 -- (b7)
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
NOTES: 1. To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (the TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register. 3. The IOA3 bit is enabled in the TRDIORA0 register only. Set to the IOA3 bit in TRDIORA1 to 1. 4. The IOA3 bit is enabled w hen the IOA2 bit is set to 1 (input capture function).
Figure 14.38
Registers TRDIORA0 to TRDIORA1 in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 189 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD I/O Control Register Ci (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
11
11
Symbol TRDIORC0 TRDIORC1 Bit Symbol
Address 0142h 0152h Bit Name TRDGRC control bits
b1 b0
After Reset 10001000b 10001000b Function 0 0 : Input capture to the TRDGRCi register at the rising edge 0 1 : Input capture to the TRDGRCi register at the falling edge 1 0 : Input capture to the TRDGRCi register at both edges 1 1 : Do not set. RW
IOC0
RW
IOC1
RW
IOC2 IOC3
TRDGRC mode select bit(1) TRDGRC register function select bit TRDGRD control bits
Set to 1 (input capture) in the input capture function. Set to 1 (general register or buffer register) in the input capture function.
b5 b4
RW RW
IOD0
IOD1
0 0 : Input capture to the TRDGRDi register at the rising edge 0 1 : Input capture to the TRDGRDi register at the falling edge 1 0 : Input capture to the TRDGRDi register at both edges 1 1 : Do not set. TRDGRD mode select bit(2) TRDGRD register function select bit Set to 1 (input capture) in the input capture function. Set to 1 (general register or buffer register) in the input capture function.
RW
RW
IOD2 IOD3
RW RW
NOTES: 1. To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (the TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
Figure 14.39
Registers TRDIORC0 to TRDIORC1 in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 190 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSR0 TRDSR1 Bit Symbol
Address 0143h 0153h Bit Name Input capture/compare match flag A
After Reset 11100000b 11000000b Function [Source for setting this bit to 0] Write 0 after read(2) [Source for setting this bit to 1] TRDSR0 register: fOCO128 signal edge w hen the IOA3 bit in the TRDIORA0 register is set to 0 (fOCO128 signal) TRDIOA0 pin input edge w hen the IOA3 bit in the TRDIORA0 register is set to 1 (TRDIOA0 input)(3) TRDSR1 register: Input edge of TRDIOA1 pin(3) RW
IMFA
RW
IMFB
Input capture/compare match flag B
[Source for setting this bit to 0] Write 0 after read(2) [Source for setting this bit to 1] Input edge of TRDIOBi pin(3) [Source for setting this bit to 0] Write 0 after read(2) [Source for setting this bit to 1] Input edge of TRDIOCi pin(4) [Source for setting this bit to 0] Write 0 after read(2) [Source for setting this bit to 1] Input edge of TRDIODi pin(4) [Source for setting this bit to 0] Write 0 after read(2) [Source for setting this bit to 1] When the TRDi register overflow s This bit is disabled in the input capture function.
RW
IMFC
Input capture/compare match flag C
RW
IMFD
Input capture/compare match flag D
RW
Overflow flag OVF
RW
UDF -- (b7-b6)
Underflow flag(1)
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
NOTES: 1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1. 2. The w riting results are as follow s: * This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. * This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) * This bit remains unchanged if 1 is w ritten to it. 3. Edge selected by bits IOj1 to IOj0 (j = A or B) in the TRDIORAi register. 4. Edge selected by bits IOk1 to IOk0 (k = C or D) in the TRDIORCi register Including w hen the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as the buffer register).
Figure 14.40
Registers TRDSR0 to TRDSR1 in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 191 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDIER0 TRDIER1 Bit Symbol IMIEA IMIEB IMIEC IMIED OVIE -- (b7-b5)
Address 0144h 0154h Bit Name Input capture/compare match interrupt enable bit A Input capture/compare match interrupt enable bit B Input capture/compare match interrupt enable bit C Input capture/compare match interrupt enable bit D Overflow /underflow interrupt enable bit
After Reset 11100000b 11100000b Function 0 : Disable interrupt (IMIA) by the IMFA bit 1 : Enable interrupt (IMIA) by the IMFA bit 0 : Disable interrupt (IMIB) by the IMFB bit 1 : Enable interrupt (IMIB) by the IMFB bit 0 : Disable interrupt (IMIC) by the IMFC bit 1 : Enable interrupt (IMIC) by the IMFC bit 0 : Disable interrupt (IMID) by the IMFD bit 1 : Enable interrupt (IMID) by the IMFD bit 0 : Disable interrupt (OVI) by the OVF bit 1 : Enable interrupt (OVI) by the OVF bit RW RW RW RW RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Figure 14.41
Registers TRDIER0 to TRDIER1 in Input Capture Function
Timer RD Counter i (i = 0 or 1)(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRD0 TRD1
Address 0147h-0146h 0157h-0156h
After Reset 0000h 0000h Setting Range 0000h to FFFFh RW RW
Function Count the count source. Count operation is incremented. When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. NOTE: 1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
Figure 14.42
Registers TRD0 to TRD1 in Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 192 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1
Address 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh
After Reset FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW RW
Function Refer to Table 14.24 TRDGRji Register Functions in Input Capture Function. NOTE: 1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.43
Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Input Capture Function
The following registers are disabled in the input capture function: TRDOER1, TRDOER2, TRDOCR, TRDPOCR0, and TRDPOCR1. Table 14.24 Register TRDGRAi TRDGRBi TRDGRCi TRDGRDi TRDGRCi TRDGRDi BFCi = 0 BFDi = 0 BFCi = 1 BFDi = 1 TRDGRji Register Functions in Input Capture Function Setting - Register Function General register The value in the TRDi register can be read at input capture. General register The value in the TRDi register can be read at input capture. Buffer register The value in the TRDi register can be read at input capture. (Refer to 14.3.2 Buffer Operation.) Input-Capture Input Pin TRDIOAi TRDIOBi TRDIOCi TRDIODi TRDIOAi TRDIOBi
i = 0 or 1, j = either A, B, C, or D BFCi, BFDi: Bits in TRDMR register Set the pulse width of the input capture signal applied to the TRDIOji pin to 3 cycles or more of the timer RD operation clock (refer to Table 14.11 Timer RD Operation Clocks) for no digital filter (the DFj bit in the TRDDFi register set to 0).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 193 of 485
R8C/24 Group, R8C/25 Group
14. Timers
TRDCLK input count source Count value in TRDi register FFFFh 0009h
0006h
0000h TSTARTi bit in TRDSTR register 1 0 65536 TRDIOAi input
TRDGRAi register Transfer TRDGRCi register
0006h
0009h Transfer 0006h
IMFA bit in TRDSRi register OVF bit in TRDSRi register
1 0 1 0 Set to 0 by a program
i = 0 or 1 The above applies under the following conditions: Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b. (the TRDi register set to 0000h by TRDGRAi register input capture). Bits TCK2 to TCK0 in the TRDCRi register are set to 101b (TRDCLK input for the count source). Bits CKEG1 to CKEG0 in the TRDCRi register are set to 01b (count at the falling edge for the count source). Bits IOA2 to IOA0 in the TRDIORAi register are set to 101b (input capture at the falling edge of the TRDIOAi input). The BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register).
Figure 14.44
Operating Example of Input Capture Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 194 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.5.1
Digital Filter
The TRDIOji input is sampled, and when the sampled input level matches 3 times, its level is determined. Select the digital filter function and sampling clock by the TRDDFi register.
TCK2 to TCK0 fOCO40M TRDCLK f32 f8 f4 f2 f1 = 101b = 100b = 011b Count source = 010b = 001b = 000b = 110b f32 f8 f1
DFCK1 to DFCK0 = 00b = 01b = 10b = 11b
IOA2 to IOA0 IOB2 to IOB0 IOC3 to IOC0 IOD3 to IOD0 Sampling clock DFj
C TRDIOji input signal D Latch Timer RD operation clock f1, fOCO40M) C D Latch Q Q D
C Q Latch D
C Q Latch D
C Q Latch
1
Match detection circuit Edge detection circuit
0
Clock period selected by bits TCK2 to TCK0 or bits DFCK1 to DFCK0
Sampling clock
TRDIOji input signal Recognition of the signal change with 3-time match Signal transmission delayed up to 5-sampling clock Transmission cannot be performed without 3-time match because the input signal is assumed to be noise. i = 0 or 1, j = either A, B, C, or D TCK0 to TCK2: Bits in TRDCRi register DFCK0 to DFCK1 and DFj: Bits in TRDDF register IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register
Input signal through digital filtering
Figure 14.45
Block Diagram of Digital Filter
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 195 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.6
Output Compare Function
This function detects matches (compare match) between the content of the TRDGRji (j = either A, B, C, or D) register and the content of the TRDi (i = 0 or 1) register. When the content matches, a user-set level is output from the TRDIOji pin. Since this function is enabled with a combination of the TRDIOji pin and TRDGRji register, the output compare function, or any other mode or function, can be selected for each individual pin. Figure 14.46 shows a Block Diagram of Output Compare Function, Table 14.25 lists the Output Compare Function Specifications. Figures 14.47 to 14.58 list the Registers Associated with Output Compare Function, and Figure 14.59 shows an Operating Example of Output Compare Function.
Channel 0
TRD0 Compare match signal Output control
TRDIOA0
IOC3 = 0 in TRDIORC0 register
Comparator
TRDGRA0
Compare match signal
TRDIOC0
Output control
IOC3 = 1
Comparator Compare match signal
TRDGRC0
TRDIOB0
Output control
IOD3 = 0 in TRDIORD0 register
Comparator
TRDGRB0
Compare match signal
TRDIOD0
Output control
IOD3 = 1
Comparator
TRDGRD0
Channel 1
TRD1 Compare match signal Output control
TRDIOA1
IOC3 = 0 in TRDIORC1 register
Comparator
TRDGRA1
Compare match signal
TRDIOC1
Output control
IOC3 = 1
Comparator Compare match signal
TRDGRC1
TRDIOB1
Output control
IOD3 = 0 in TRDIORD1 register
Comparator
TRDGRB1
Compare match signal
TRDIOD1
Output control
IOD3 = 1
Comparator
TRDGRD1
Figure 14.46
Block Diagram of Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 196 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.25
Output Compare Function Specifications
Specification f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Count operations Increment Count period * When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (freerunning operation) 1/fk x 65536 fk: Frequency of count source * Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (set the TRDi register to 0000h at the compare match in the TRDGRji register). Frequency of count source x (n+1) n: Setting value in the TRDGRji register Waveform output timing Compare match Count start condition 1 (count starts) is written to the TSTARTi bit in the TRDSTR register. Count stop conditions * 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. The output compare output pin holds output level before the count stops. * When the CSELi bit in the TRDSTR register is set to 0, the count stops at the compare match in the TRDGRAi register. The output compare output pin holds level after output change by the compare match. Interrupt request generation * Compare match (content of the TRDi register matches content of the TRDGRji timing register.) * TRDi register overflows TRDIOA0 pin function Programmable I/O port, output-compare output, or TRDCLK (external clock) input TRDIOB0, TRDIOC0, TRDIOD0, Programmable I/O port or output-compare output (Selectable by pin) TRDIOA1 to TRDIOD1 pin functions INT0 pin function Read from timer Write to timer Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRDi register. * When the SYNC bit in the TRDMR register is set to 0 (channels 0 and 1 operate independently). Data can be written to the TRDi register. * When the SYNC bit in the TRDMR register is set to 1 (channels 0 and 1 operate synchronously). Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi register. * Output-compare output pin selected Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi. * Output level at the compare match selected "L" output, "H" output, or output level inversed * Initial output level selected Set the level at period from the count start to the compare match. * Timing to set the TRDi register to 0000h Overflow or compare match in the TRDGRAi register * Buffer operation (Refer to 14.3.2 Buffer Operation.) * Synchronous operation (Refer to 14.3.3 Synchronous Operation.) * Output pin in registers TRDGRCi and TRDGRDi changed The TRDGRCi register can be used as output control of the TRDIOAi pin and the TRDGRDi register can be used as output control of the TRDIOBi pin. * Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output Forced Cutoff.) * Timer RD can be used as the internal timer without output.
Item Count sources
Select functions
i = 0 or 1, j = either A, B, C, or D
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 197 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSTR Bit Symbol TSTART0 TSTART1
Address 0137h Bit Name TRD0 count start flag(4) TRD1 count start flag(5) TRD0 count operation select bit
After Reset 11111100b Function 0 : Count stops (2) 1 : Count starts 0 : Count stops (3) 1 : Count starts 0 : Count stops at the compare match w ith the TRDGRA0 register 1 : Count continues at the compare match w ith the TRDGRA0 register 0 : Count stops at the compare match w ith the TRDGRA1 register 1 : Count continues at the compare match w ith the TRDGRA1 register
RW RW RW
CSEL0
RW
CSEL1
TRD1 count operation select bit
RW
-- (b7-b4)
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
--
NOTES: 1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Register of Notes on Tim er RD. 2. When the CSEL0 bit is 3. When the CSEL1 bit is 4. When the CSEL0 bit is stops). 5. When the CSEL1 bit is stops). set to 1, w rite 0 to the TSTART0 bit. set to 1, w rite 0 to the TSTART1 bit. set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDMR Bit Symbol
Address 0138h Bit Name Timer RD synchronous bit
SYNC
After Reset 00001110b Function 0 : Registers TRD0 and TRD1 operate independently 1 : Registers TRD0 and TRD1 operate synchronously
RW
RW
-- (b3-b1) BFC0 BFD0 BFC1 BFD1
Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select 0 : General register 1 : Buffer register of TRDGRA0 register bit(1) TRDGRD0 register function select 0 : General register bit(1) 1 : Buffer register of TRDGRB0 register TRDGRC1 register function select 0 : General register bit(1) 1 : Buffer register of TRDGRA1 register TRDGRD1 register function select 0 : General register 1 : Buffer register of TRDGRB1 register bit(1)
-- RW RW RW RW
NOTE: 1. When selecting 0 (change the TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi (i = 0 or 1) register, set the BFji bit in the TRDMR register to 0.
Figure 14.47
Registers TRDSTR and TRDMR in Output Compare Function Page 198 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD PWM Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
000
000
Symbol TRDPMR Bit Symbol PWMB0 PWMC0 PWMD0 -- (b3) PWMB1 PWMC1 PWMD1 -- (b7)
Address 0139h Bit Name PWM mode of TRDIOB0 select bit PWM mode of TRDIOC0 select bit PWM mode of TRDIOD0 select bit
After Reset 10001000b Function Set to 0 (timer mode) in the output compare function. Set to 0 (timer mode) in the output compare function. Set to 0 (timer mode) in the output compare function.
RW RW RW RW -- RW RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1. PWM mode of TRDIOB1 select bit PWM mode of TRDIOC1 select bit PWM mode of TRDIOD1 select bit Set to 0 (timer mode) in the output compare function. Set to 0 (timer mode) in the output compare function. Set to 0 (timer mode) in the output compare function.
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Figure 14.48
TRDPMR Register in Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 199 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
1
00
Symbol TRDFCR Bit Symbol CMD0 CMD1
Address 013Ah Bit Name Combination mode select bits (1)
After Reset 10000000b Function Set to 00b (timer mode, PWM mode, or PWM3 mode) in the output compare function.
RW RW RW
OLS0
Normal-phase output level select bit This bit is disabled in the output compare (in reset synchronous PWM mode or function. complementary PWM mode) Counter-phase output level select bit This bit is disabled in the output compare (in reset synchronous PWM mode or function. complementary PWM mode) A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) External clock input select bit PWM3 mode select bit(2) This bit is disabled in the output compare function. This bit is disabled in the output compare function. 0 : External clock input disabled 1 : External clock input enabled Set this bit to 1 (other than PWM3 mode) in the output compare function.
RW
OLS1
RW
ADTRG ADEG STCLK PWM3
RW RW RW RW
NOTES: 1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled.
Figure 14.49
TRDFCR Register in Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 200 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol TRDOER1 Bit Symbol EA0
Address 013Bh Bit Name TRDIOA0 output disable bit
After Reset FFh Function 0 : Enable output 1 : Disable output (The TRDIOA0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOB0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOC0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOD0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOA1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOB1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOC1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOD1 pin is used as a programmable I/O port.)
RW RW
TRDIOB0 output disable bit EB0 TRDIOC0 output disable bit EC0 TRDIOD0 output disable bit ED0 TRDIOA1 output disable bit EA1 TRDIOB1 output disable bit EB1 TRDIOC1 output disable bit EC1 TRDIOD1 output disable bit ED1
RW
RW
RW
RW
RW
RW
RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 013Ch TRDOER2 Bit Symbol Bit Name -- Nothing is assigned. If necessary, set to 0. (b6-b0) When read, the content is 1.
_____
After Reset 01111111b Function
RW --
PTO
INT0 of pulse output forced cutoff signal input enabled bit(1)
0 : Pulse output forced cutoff input disabled 1 : Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (disable output) w hen "L" is
_____
RW
applied to the INT0 pin.) NOTE: 1. Refer to 14.3.4 Pulse Output Forced Cutoff.
Figure 14.50
Registers TRDOER1 to TRDOER2 in Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 201 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Output Control Register(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
001
Symbol TRDOCR Bit Symbol TOA0 TOB0 TOC0 TOD0 TOA1 TOB1 TOC1 TOD1
Address 013Dh Bit Name TRDIOA0 output level select bit TRDIOB0 output level select bit TRDIOC0 initial output level select bit TRDIOD0 initial output level select bit TRDIOA1 initial output level select bit TRDIOB1 initial output level select bit TRDIOC1 initial output level select bit TRDIOD1 initial output level select bit
After Reset 00h Function 0 : Initial output "L" 1 : Initial output "H" 0 : Initial output "L" 1 : Initial output "H" 0 : "L" 1 : "H"
RW RW RW RW RW RW RW RW RW
NOTES: 1. Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stopped). 2. If the pin function is set for w aveform output (refer to Tables 14.12 to 14.19), the initial output level is output w hen the TRDOCR register is set.
Figure 14.51
TRDOCR Register in Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 202 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDCR0 TRDCR1 Bit Symbol TCK0
Address 0140h 0150h Bit Name Count source select bits
b2 b1 b0
After Reset 00h 00h Function 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : TRDCLK input(1) 0 : fOCO40M 1 : Do not set. RW RW
TCK1
RW
TCK2 External clock edge select bits (2)
RW
b4 b3
CKEG0
CKEG1 TRDi counter clear select bits CCLR0
0 0 1 1
0 : Count at the rising edge 1 : Count at the falling edge 0 : Count at both edges 1 : Do not set.
RW
RW
b7 b6 b5
CCLR1
CCLR2
0 0 0 : Disable clear (free-running operation) 0 0 1 : Clear by compare match w ith the TRDGRAi register 0 1 0 : Clear by compare match w ith the TRDGRBi register 0 1 1 : Synchronous clear (clear simultaneously w ith other channel counter)(3) 1 0 0 : Do not set. 1 0 1 : Clear by compare match w ith the TRDGRCi register 1 1 0 : Clear by compare match w ith the TRDGRDi register 1 1 1 : Do not set.
RW
RW
RW
NOTES: 1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 3. This setting is enabled w hen the SYNC bit in the TRDMR register is set to 1 (TRD0 and TRD1 operate synchronously).
Figure 14.52
Registers TRDCR0 to TRDCR1 in Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 203 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD I/O Control Register Ai (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol TRDIORA0 TRDIORA1 Bit Symbol
Address 0141h 0151h Bit Name TRDGRA control bits
b1 b0
After Reset 10001000b 10001000b Function 0 0 : Disable pin output by the compare match (TRDIOAi pin functions as programmable I/O port) 0 1 : "L" output at compare match w ith the TRDGRAi register 1 0 : "H" output at compare match w ith the TRDGRAi register 1 1 : Toggle output by compare match w ith the TRDGRAi register RW
IOA0
RW
IOA1
RW
IOA2 IOA3
TRDGRA mode select bit(1) Set to 0 (output compare) in the output compare function. Input capture input sw itch bit TRDGRB control bits Set to 1.
b5 b4
RW RW
IOB0
IOB1
0 0 : Disable pin output by the compare match (TRDIOBi pin functions as programmable I/O port) 0 1 : "L" output at compare match w ith the TRDGRBi register 1 0 : "H" output at compare match w ith the TRDGRBi 1 1 : Toggle output by compare match w ith the TRDGRBi register TRDGRB mode select bit(2) Set to 0 (output compare) in the output compare function.
RW
RW
IOB2 -- (b7)
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
NOTES: 1. To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (the TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
Figure 14.53
Registers TRDIORA0 to TRDIORA1 in Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 204 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD I/O Control Register Ci (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol TRDIORC0 TRDIORC1 Bit Symbol
Address 0142h 0152h Bit Name TRDGRC control bits
b1 b0
After Reset 10001000b 10001000b Function 0 0 : Disable pin output by compare match 0 1 : "L" output at compare match w ith the TRDGRCi register 1 0 : "H" output at compare match w ith the TRDGRCi register 1 1 : Toggle output by compare match w ith the TRDGRCi register RW
IOC0
RW
IOC1
RW
IOC2
TRDGRC mode select bit(1) TRDGRC register function select bit
Set to 0 (output compare) in the output compare function. 0 : TRDIOA output register (Refer to 14.3.6.1 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi.) 1 : General register or buffer register
b5 b4
RW
IOC3
RW
TRDGRD control bits IOD0
IOD1
0 0 : Disable pin output by compare match 0 1 : "L" output at compare match w ith the TRDGRDi register 1 0 : "H" output at compare match w ith the TRDGRDi register 1 1 : Toggle output by compare match w ith the TRDGRDi register TRDGRD mode select bit(2) TRDGRD register function select bit Set to 0 (output compare) in the output compare function. 0 : TRDIOB output register (Refer to 14.3.6.1 Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi.) 1 : General register or buffer register
RW
RW
IOD2
RW
IOD3
RW
NOTES: 1. To select 1 (the TRDGRCi register is used as a buffer register of the TRDGRAi register) for this bit by the BFCi bit in the TRDMR register, set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register. 2. To select 1 (the TRDGRDi register is used as a buffer register of the TRDGRBi register) for this bit by the BFDi bit in the TRDMR register, set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register.
Figure 14.54
Registers TRDIORC0 to TRDIORC1 in Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 205 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Status Register i (i=0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSR0 TRDSR1 Bit Symbol
Address 0143h 0153h
After Reset 11100000b 11000000b RW
IMFA
Bit Name Function Input capture/compare match [Source for setting this bit to 0] flag A Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. Input capture/compare match [Source for setting this bit to 0] flag B Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. Input capture/compare match [Source for setting this bit to 0] flag C Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register (3). Input capture/compare match [Source for setting this bit to 0] flag D Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register (3). Overflow flag [Source for setting this bit to 0] Write 0 after read(2). [Source for setting this bit to 1] When the TRDi register overflow s. This bit is disabled in the output compare function.
RW
IMFB
RW
IMFC
RW
IMFD
RW
OVF
RW
UDF -- (b7-b6)
Underflow flag(1)
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
NOTES: 1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1. 2. The w riting results are as follow s: * This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. * This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) * This bit remains unchanged if 1 is w ritten to it. 3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.55
Registers TRDSR0 to TRDSR1 in Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 206 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDIER0 TRDIER1 Bit Symbol
Address 0144h 0154h Bit Name Input capture/compare match interrupt enable bit A
After Reset 11100000b 11100000b Function 0 : Disable interrupt (IMIA) by the IMFA bit 1 : Enable interrupt (IMIA) by the IMFA bit 0 : Disable interrupt (IMIB) by the IMFB bit 1 : Enable interrupt (IMIB) by the IMFB bit 0 : Disable interrupt (IMIC) by the IMFC bit 1 : Enable interrupt (IMIC) by the IMFC bit 0 : Disable interrupt (IMID) by the IMFD bit 1 : Enable interrupt (IMID) by the IMFD bit RW
IMIEA
RW
IMIEB
Input capture/compare match interrupt enable bit B
RW
IMIEC
Input capture/compare match interrupt enable bit C
RW
IMIED
Input capture/compare match interrupt enable bit D
RW
OVIE
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the bit OVF bit 1 : Enable interrupt (OVI) by the OVF bit Nothing is assigned. If necessary, set to 0. When read, the content is 1.
RW
-- (b7-b5)
--
Figure 14.56
Registers TRDIER0 to TRDIER1 in Output Compare Function
Timer RD Counter i (i = 0 or 1)(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRD0 TRD1
Address 0147h-0146h 0157h-0156h
After Reset 0000h 0000h Setting Range 0000h to FFFFh RW RW
Function Count a count source. Count operation is incremented. When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. NOTE: 1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
Figure 14.57
Registers TRD0 to TRD1 in Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 207 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD General Register Ai, Bi, Ci and Di (i = 0 or 1)(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1
Address 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh
After Reset FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW RW
Function Refer to Table 14.26 TRDGRji Register Function in Output Com pare Function. NOTE: 1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.58
Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Output Compare Function
The following registers are disabled in the output compare function: TRDDF0, TRDDF1, TRDPOCR0, and TRDPOCR1. Table 14.26 Register TRDGRAi TRDGRBi TRDGRCi TRDGRDi TRDGRCi TRDGRDi TRDGRCi TRDGRDi TRDGRji Register Function in Output Compare Function Setting BFji IOj3 - - 0 1 0 1 1 0 Output-Compare Output Pin General register. Write the compare value. TRDIOAi TRDIOBi General register. Write the compare value. TRDIOCi TRDIODi Buffer register. Write the next compare value. TRDIOAi (Refer to 14.3.2 Buffer Operation.) TRDIOBi TRDIOAi output control. (Refer to 14.3.6.1 Changing TRDIOAi Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDIOBi TRDGRDi.) Register Function
i = 0 or 1, j = either A, B, C, or D BFji: Bit in TRDMR register IOj3: Bit in TRDIORCi register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 208 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Count source Value in TRDi register m
n
p Count restarts Count stops TSTARTi bit in TRDSTR register 1 0 m+1 m+1 Output level held TRDIOAi output Output inverted by compare match Initial output "L" IMFA bit in TRDSRi register 1 0 Set to 0 by a program n+1 TRDIOBi output n+1 Initial output "L" IMFB bit in TRDSRi register 1 0 Set to 0 by a program P+1 "L" output by compare match TRDIOCi output Initial output "H" Output level held "H" output by compare match Output level held
IMFC bit in TRDSRi register
1 0 Set to 0 by a program
i = 0 or 1
M: Value set in TRDGRAi register n: Value set in TRDGRBi register p: Value set in TRDGRCi register
The above applies under the following conditions: The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match). Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers). Bits EAi, EBi, and ECi in the TRDOER1 register are set to 0 (enable the TRDIOAi, TRDIOBi and TRDIOCi pin outputs). Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 000h by compare match in the TRDGRAi register). Bits TOAi and TOBi in the TRDOCR register is set to 0 (initial output "L" to compare match), the TOCi bit is set to 1 (initial output "H" to compare match). Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match). Bits IOB2 to IOB0 in the TRDIORAi register are set to 010b (TRDIOBi "H" output at TRDGRBi register compare match). Bits IOC3 to IOC0 in the TRDIORCi register are set to 1001b (TRDIOCi "L" output at TRDGRCi register compare match). The IOD3 bit in the TRDIORCi register is set to 1 (TRDGRDi register does not control TRDIOBi pin output).
Figure 14.59
Operating Example of Output Compare Function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 209 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.6.1
Changing Output Pins in Registers TRDGRCi (i = 0 or 1) and TRDGRDi
The TRDGRCi register can be used for output control of the TRDIOAi pin, and the TRDGRDi register can be used for output control of the TRDIOBi pin. Therefore, each pin output can be controlled as follows: * TRDIOAi output is controlled by the values in registers TRDGRAi and TRDGRCi. * TRDIOBi output is controlled by the values in registers TRDGRBi and TRDGRDi. Change output pins in registers TRDGRCi and TRDGRDi as follows: * Select 0 (change TRDGRji register output pin) by the IOj3 (j = C or D) bit in the TRDIORCi register. * Set the BFji bit in the TRDMR register to 0 (general register). * Set different values in registers TRDGRCi and TRDGRAi. Also, set different values in registers TRDGRDi and TRDGRBi. Figure 14.61 shows an Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 210 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Channel 0
TRD0 Compare match signal Output control
TRDIOA0
IOC3 = 0 in TRDIORC0 register
Comparator
TRDGRA0
Compare match signal
TRDIOC0
Output control
IOC3 = 1
Comparator Compare match signal
TRDGRC0
TRDIOB0
Output control
IOD3 = 0 in TRDIORD0 register
Comparator
TRDGRB0
Compare match signal
TRDIOD0
Output control
IOD3 = 1
Comparator
TRDGRD0
Channel 1
TRD1 Compare match signal Output control
TRDIOA1
IOC3 = 0 in TRDIORC1 register
Comparator
TRDGRA1
Compare match signal
TRDIOC1
Output control
IOC3 = 1
Comparator Compare match signal
TRDGRC1
TRDIOB1
Output control
IOD3 = 0 in TRDIORD1 register
Comparator
TRDGRB1
Compare match signal
TRDIOD1
Output control
IOD3 = 1
Comparator
TRDGRD1
Figure 14.60
Changing Output Pins in Registers TRDGRCi and TRDGRDi
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 211 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Count source Value in TRDi register FFFFh m
n
p
q
0000h m+1 n+1 p+1 q+1 Initial output "L" TRDIOAi output Output inverted by compare match IMFA bit in TRDSRi register 1 0 Set to 0 by a program IMFC bit in TRDSRi register 1 0 Set to 0 by a program p-q m-n
Initial output "L" TRDIOBi output Output inverted by compare match IMFB bit in TRDSRi register 1 0
Set to 0 by a program IMFD bit in TRDSRi register 1 0
Set to 0 by a program
i = 0 or 1
m: Value set in TRDGRAi register n: Value set in TRDGRCi register p: Value set in TRDGRBi register q: Value set in TRDGRDi register
The above applies under the following conditions: The CSELi bit in the TRDSTR register is set to 1 (the TRDi register is not stopped by compare match). Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer register). Bits EAi and EBi in the TRDOER1 register are set to 0 (enable TRDIOAi and TRDIOBi pin outputs). Bits CCLR2 to CCLR0 in the TRDCRi register are set to 001b (set the TRDi register to 0000h by compare match in the TRDGRAi register). Bits TOAi and TOBi in the TRDOCR register are set to 0 (initial output "L" to compare match). Bits IOA2 to IOA0 in the TRDIORAi register are set to 011b (TRDIOAi output inverted at TRDGRAi register compare match). Bits IOB2 to IOB0 in the TRDIORAi register are set to 011b (TRDIOBi output inverted at TRDGRBi register compare match). Bits IOC3 to IOC0 in the TRDIORCi register are set to 0011b (TRDIOAi output inverted at TRDGRCi register compare match). Bits IOD3 to IOD0 in the TRDIORCi register are set to 0011b (TRDIOBi output inverted at TRDGRDi register compare match).
Figure 14.61
Operating Example When TRDGRCi Register is Used for Output Control of TRDIOAi Pin and TRDGRDi Register is Used for Output Control of TRDIOBi Pin
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 212 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.7
PWM Mode
In PWM mode, a PWM waveform is output. Up to 3 PWM waveforms with the same period can be output by 1 channel. Also, up to 6 PWM waveforms with the same period can be output by synchronizing channels 0 and 1. Since this mode functions by a combination of the TRDIOji (i = 0 or 1, j = B, C, or D) pin and TRDGRji register, the PWM mode, or any other mode or function, can be selected for each individual pin. (However, since the TRDGRAi register is used when using any pin for PWM mode, the TRDGRAi register cannot be used for other modes.) Figure 14.62 shows a Block Diagram of PWM Mode, and Table 14.27 lists the PWM Mode Specifications. Figures 14.63 to 14.72 show the Registers Associated with PWM Mode, and Figures 14.73 and 14.74 show Operating Examples of PWM Mode.
TRDi Compare match signal
TRDIOBi
Compare match signal
Comparator
TRDGRAi (Note 1)
TRDIOCi
Output control
Comparator Compare match signal
TRDGRBi
TRDIODi
Compare match signal
Comparator
TRDGRCi (Note 2)
Comparator
TRDGRDi
i = 0 or 1 NOTES: 1. When the BFCi bit in the TRDMR register is set to 1 (the TRDGRCi register is used as the buffer register of the TRDGRAi register). 2. When the BFDi bit in the TRDMR register is set to 1 (the TRDGRDi register is used as the buffer register of the TRDGRBi register).
Figure 14.62
Block Diagram of PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 213 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.27
PWM Mode Specifications Specification f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Increment PWM period: 1/fk x (m+1) Active level width: 1/fk x (m-n) Inactive level width: 1/fk x (n+1) fk: Frequency of count source m: Value set in the TRDGRAi register n: Value set in the TRDGRji register
m+1
Item Count sources
Count operations PWM waveform
n+1
m-n
(When "L" is selected as the active level)
1 (count starts) is written to the TSTARTi bit in the TRDSTR register. * 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the CSELi bit in the TRDSTR register is set to 1. The PWM output pin holds output level before the count stops. * When the CSELi bit in the TRDSTR register is set to 0, the count stops at the compare match in the TRDGRAi register. The PWM output pin holds level after output change by compare match. * Compare match (The content of the TRDi register matches content of Interrupt request generation timing the TRDGRhi register.) * TRDi register overflows TRDIOA0 pin function Programmable I/O port or TRDCLK (external clock) input TRDIOA1 pin function Programmable I/O port TRDIOB0, TRDIOC0, TRDIOD0, Programmable I/O port or pulse output (selectable by pin) TRDIOB1, TRDIOC1, TRDIOD1 pin functions INT0 pin function Read from timer Write to timer Select functions Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRDi register. The value can be written to the TRDi register. * 1 to 3 PWM output pins selected per 1 channel Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi pin. * The active level selected by pin. * Initial output level selected by pin. * Synchronous operation (Refer to 14.3.3 Synchronous Operation.) * Buffer operation (Refer to 14.3.2 Buffer Operation.) * Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output Forced Cutoff.)
Count start condition Count stop conditions
i = 0 or 1 j = either B, C, or D h = either A, B, C, or D
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 214 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSTR Bit Symbol TSTART0 TSTART1
Address 0137h Bit Name TRD0 count start flag(4) TRD1 count start flag(5)
After Reset 11111100b Function 0 : Count stops (2) 1 : Count starts 0 : Count stops (3) 1 : Count starts
RW RW RW
CSEL0
TRD0 count operation select bit 0 : Count stops at compare match w ith the TRDGRA0 register 1 : Count continues at compare match w ith the TRDGRA0 register TRD1 count operation select bit 0 : Count stops at compare match w ith the TRDGRA1 register 1 : Count continues at compare match w ith the TRDGRA1 register Nothing is assigned. If necessary, set to 0. When read, the content is 1.
RW
CSEL1
RW
-- (b7-b4)
--
NOTES: 1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Register of Notes on Tim er RD. 2. When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit. 3. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit. 4. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 5. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count stops).
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDMR Bit Symbol
Address 0138h Bit Name Timer RD synchronous bit
SYNC
After Reset 00001110b Function 0 : Registers TRD0 and TRD1 operate independently 1 : Registers TRD0 and TRD1 operate synchronously
RW
RW
-- (b3-b1) BFC0 BFD0 BFC1 BFD1
Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select bit TRDGRD0 register function select bit TRDGRC1 register function select bit TRDGRD1 register function select bit 0 : General register 1 : Buffer register of TRDGRA0 register 0 : General register 1 : Buffer register of TRDGRB0 register 0 : General register 1 : Buffer register of TRDGRA1 register 0 : General register 1 : Buffer register of TRDGRB1 register
-- RW RW RW RW
Figure 14.63
Registers TRDSTR and TRDMR in PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 215 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD PWM Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDPMR Bit Symbol PWMB0 PWMC0 PWMD0 -- (b3) PWMB1 PWMC1 PWMD1 -- (b7)
Address 0139h Bit Name PWM mode of TRDIOB0 select bit PWM mode of TRDIOC0 select bit PWM mode of TRDIOD0 select bit
After Reset 10001000b Function 0 : Timer mode 1 : PWM mode 0 : Timer mode 1 : PWM mode 0 : Timer mode 1 : PWM mode
RW RW RW RW -- RW RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1. PWM mode of TRDIOB1 select bit PWM mode of TRDIOC1 select bit PWM mode of TRDIOD1 select bit 0 : Timer mode 1 : PWM mode 0 : Timer mode 1 : PWM mode 0 : Timer mode 1 : PWM mode
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Figure 14.64
TRDPMR Register in PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 216 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
1
00
Symbol TRDFCR Bit Symbol CMD0 CMD1
Address 013Ah Bit Name Combination mode select bits (1)
After Reset 10000000b Function Set to 00b (timer mode, PWM mode, or PWM3 mode) in PWM mode.
RW RW RW
OLS0
Normal-phase output level select Bit This bit is disabled in PWM mode. (in reset synchronous PWM mode or complementary PWM mode) Counter-phase output level select bit This bit is disabled in PWM mode. (in reset synchronous PWM mode or complementary PWM mode) A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) External clock input select bit PWM3 mode select bit(2) This bit is disabled in PWM mode. This bit is disabled in PWM mode. 0 : External clock input disabled 1 : External clock input enabled Set this bit to 1 (other than PWM3 mode) in PWM mode.
RW
OLS1
RW
ADTRG ADEG STCLK PWM3
RW RW RW RW
NOTES: 1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled.
Figure 14.65
TRDFCR Register in PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 217 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Symbol TRDOER1 Bit Symbol EA0
Address 013Bh Bit Name TRDIOA0 output disable bit
After Reset FFh Function 0 : Enable output 1 : Disable output (The TRDIOA0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOB0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOC0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOD0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOA1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOB1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOC1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOD1 pin is used as a programmable I/O port.)
RW RW
TRDIOB0 output disable bit EB0 TRDIOC0 output disable bit EC0 TRDIOD0 output disable bit ED0 TRDIOA1 output disable bit EA1 TRDIOB1 output disable bit EB1 TRDIOC1 output disable bit EC1 TRDIOD1 output disable bit ED1
RW
RW
RW
RW
RW
RW
RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 013Ch TRDOER2 Bit Symbol Bit Name -- Nothing is assigned. If necessary, set to 0. (b6-b0) When read, the content is 1.
_____
After Reset 01111111b Function
RW --
PTO
INT0 of pulse output forced 0 : Pulse output forced cutoff input disabled cutoff signal input enabled bit(1) 1 : Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (disable output) w hen "L" is
_____
RW
applied to the INT0 pin.) NOTE: 1. Refer to 14.3.4 Pulse Output Forced Cutoff.
Figure 14.66
Registers TRDOER1 to TRDOER2 in PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 218 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Output Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol TRDOCR Bit Symbol TOA0 TOB0 TOC0 TOD0 TOA1 TOB1 TOC1 TOD1
Address 013Dh Bit Name TRDIOA0 output level select bit TRDIOB0 output level select bit(2) TRDIOC0 initial output level select bit(2) TRDIOD0 initial output level select bit(2) TRDIOA1 initial output level select bit TRDIOB1 initial output level select bit(2) TRDIOC1 initial output level select bit(2) TRDIOD1 initial output level select bit(2)
After Reset 00h Function Set this bit to 0 (enable output) in PWM mode. 0 : Initial output is inactive level 1 : Initial output is active level Set this bit to 0 (enable output) in PWM mode. 0 : Inactive level 1 : Active level
RW RW RW RW RW RW RW RW RW
NOTES: 1. Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops). 2. If the pin function is set for w aveform output (refer to Tables 14.13 to 14.15 and Tables 14.17 to 14.19), the initial output level is output w hen the TRDOCR register is set.
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
001
Symbol TRDCR0 TRDCR1 Bit Symbol TCK0
Address 0140h 0150h Bit Name Count source select bits
b2 b1 b0
After Reset 00h 00h Function 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : TRDCLK input(1) 0 : fOCO40M 1 : Do not set. RW RW
TCK1
RW
TCK2 External clock edge select bits (2) CKEG0
RW
b4 b3
CKEG1 CCLR0 CCLR1 CCLR2 TRDi counter clear select bits
0 0 1 1
0 : Count at the rising edge 1 : Count at the falling edge 0 : Count at both edges 1 : Do not set.
RW
RW
Set to 001b (the TRDi register cleared at RW compare match w ith TRDGRAi register) in PWM RW mode. RW
NOTES: 1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Figure 14.67
Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 219 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Status Register i (i=0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSR0 TRDSR1 Bit Symbol
Address 0143h 0153h
After Reset 11100000b 11000000b RW
IMFA
Bit Name Function Input capture/compare match [Source for setting this bit to 0] flag A Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. Input capture/compare match [Source for setting this bit to 0] flag B Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. Input capture/compare match [Source for setting this bit to 0] flag C Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register (3). Input capture/compare match [Source for setting this bit to 0] flag D Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register (3). Overflow flag [Source for setting this bit to 0] Write 0 after read(2). [Source for setting this bit to 1] When the TRDi register overflow s. This bit is disabled in PWM mode.
RW
IMFB
RW
IMFC
RW
IMFD
RW
OVF
RW
UDF -- (b7-b6)
Underflow flag(1)
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
NOTES: 1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1. 2. The w riting results are as follow s: * This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. * This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0.) * This bit remains unchanged if 1 is w ritten. 3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.68
Registers TRDSR0 to TRDSR1 in PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 220 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDIER0 TRDIER1 Bit Symbol
Address 0144h 0154h Bit Name Input capture/compare match interrupt enable bit A
After Reset 11100000b 11100000b Function 0 : Disable interrupt (IMIA) by the IMFA bit 1 : Enable interrupt (IMIA) by the IMFA bit 0 : Disable interrupt (IMIB) by the IMFB bit 1 : Enable interrupt (IMIB) by the IMFB bit 0 : Disable interrupt (IMIC) by the IMFC bit 1 : Enable interrupt (IMIC) by the IMFC bit 0 : Disable interrupt (IMID) by the IMFD bit 1 : Enable interrupt (IMID) by the IMFD bit RW
IMIEA
RW
IMIEB
Input capture/compare match interrupt enable bit B
RW
IMIEC
Input capture/compare match interrupt enable bit C
RW
IMIED
Input capture/compare match interrupt enable bit D
RW
OVIE
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the bit OVF bit 1 : Enable interrupt (OVI) by the OVF bit Nothing is assigned. If necessary, set to 0. When read, the content is 1.
RW
-- (b7-b5)
--
Figure 14.69
Registers TRDIER0 to TRDIER1 in PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 221 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD PWM Mode Output Level Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDPOCR0 TRDPOCR1 Bit Symbol
Address 0145h 0155h Bit Name PWM mode output level control bit B
After Reset 11111000b 11111000b Function 0 : "L" active TRDIOBi output level is selected 1 : "H" active TRDIOBi output level is selected 0 : "L" active TRDIOCi output level is selected 1 : "H" active TRDIOCi output level is selected 0 : "L" active TRDIODi output level is selected 1 : "H" active TRDIODi output level is selected RW
POLB
RW
POLC
PWM mode output level control bit C
RW
POLD
PWM mode output level control bit D
RW
-- (b7-b3)
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
--
Figure 14.70
Registers TRDPOCR0 to TRDPOCR1 in PWM Mode
Timer RD Counter i (i = 0 or 1)(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRD0 TRD1
Address 0147h-0146h 0157h-0156h
After Reset 0000h 0000h Setting Range 0000h to FFFFh RW RW
Function Count a count source. Count operation is incremented. When an overflow occurs, the OVF bit in the TRDSRi register is set to 1. NOTE: 1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
Figure 14.71
Registers TRD0 to TRD1 in PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 222 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1
Address 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh
After Reset FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW RW
Function Refer to Table 14.28 TRDGRji Register Functions in PWM Mode. NOTE: 1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.72
Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in PWM Mode
The following registers are disabled in the PWM mode: TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDIORA1, and TRDIORC1. Table 14.28 Register TRDGRAi TRDGRBi TRDGRCi TRDGRDi TRDGRCi TRDGRDi TRDGRji Register Functions in PWM Mode Setting - - BFCi = 0 BFDi = 0 BFCi = 1 BFDi = 1 Register Function PWM Output Pin General register. Set the PWM period - General register. Set the changing point of PWM output TRDIOBi General register. Set the changing point of PWM output TRDIOCi TRDIODi - Buffer register. Set the next PWM period. (Refer to 14.3.2 Buffer Operation.) Buffer register. Set the changing point of the next PWM TRDIOBi output. (Refer to 14.3.2 Buffer Operation.)
i = 0 or 1 BFCi, BFDi: Bits in TRDMR register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 223 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Count source Value in TRDi register m
n
p
q
m+1 n+1 m-n
TRDIOBi output
Active level "H" Initial output "L" to compare match
Inactive level "L" p+1 m-p
TRDIOCi output
Initial output "H" to compare match
Inactive level "H" q+1 m-q
TRDIODi output
Active level "L"
IMFA bit in TRDSRi register
1 0
Initial output "L" to compare match
IMFB bit in TRDSRi register
1 0
Set to 0 by a program
Set to 0 by a program
IMFC bit in TRDSRi register
1 0 Set to 0 by a program Set to 0 by a program
IMFD bit in TRDSRi register
1 0
i = 0 or 1
m: Value set in TRDGRAi register n: Value set in TRDGRBi register p: Value set in TRDGRCi register q: Value set in TRDGRDi register
The above applies under the following conditions: Bits BFCi and BFDi in the TRDMR register are set to 0 (registers TRDGRCi and TRDGRDi are not used as buffer registers). Bits EBi, ECi and EDi in the TRDOER1 register are set to 0 (enable TRDIOBi, TRDIOCi and TRDIODi pin outputs). Bits TOBi and TOCi in the TRDOCR register are set to 0 (inactive level), the TODi bit is set to 1 (active level). The POLB bit in the TRDPOCRi register is set to 1 (active level "H"), bits POLC and POLD are set to 0 (active level "L").
Figure 14.73
Operating Example of PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 224 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Value in TRDi register p m
q n 0000h
TSTARTi bit in TRDSTR register
1 0 Since no compare match in the TRDGRBi register is generated, "L" is not applied to the TRDIOBi output Duty 0%
TRDIOBi output
TRDGRBi register
n
p (p>m) Rewrite by a program
q
IMFA bit in TRDSRi register
1 0 Set to 0 by a program Set to 0 by a program
IMFB bit in TRDSRi register
1 0
Value in TRDi register m
p n 0000h
TSTARTi bit in TRDSTR register
1 0
When compare matches with registers TRDGRAi and TRDGRBi are generated simultaneously, the compare match with the TRDGRBi register has priority. "L" is applied to the TRDIOBi output without any change. Duty 100% "L" is applied to TRDIOBi output at compare match with the TRDGRBi register with no change.
TRDIOBi output
TRDGRBi register
n
m Rewrite by a program
p
IMFA bit in TRDSRi register
1 0 Set to 0 by a program Set to 0 by a program
IMFB bit in TRDSRi register
1 0
i = 0 or 1
m: Value set in TRDGRAi register
The above applies under the following conditions: The EBi bit in the TRDOER1 register is set to 0 (enable TRDIOBi output). The POLB bit in the TRDPOCRi register is set to 0 (active level "L").
Figure 14.74
Operating Example of PWM Mode (Duty 0%, Duty 100%)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 225 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.8
Reset Synchronous PWM Mode
In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period (three-phase, sawtooth wave modulation, and no dead time). Figure 14.75 shows a Block Diagram of Reset Synchronous PWM Mode, and Table 14.29 lists the Reset Synchronous PWM Mode Specifications. Figures 14.76 to 14.83 show the Registers Associated with Reset Synchronous PWM Mode and Figure 14.84 shows an Operating Example of Reset Synchronous PWM Mode. Refer to Figure 14.74 Operating Example of PWM Mode (Duty 0%, Duty 100%) for an operating example of PWM Mode with duty 0% and duty 100%.
Buffer(1) TRDGRC0 register
TRDGRA0 register
Waveform control
Period
Normal-phase
TRDIOC0
TRDGRD0 register
TRDGRB0 register
TRDIOB0
PWM1
Counter-phase
TRDIOD0
Normal-phase
TRDGRC1 register
TRDGRA1 register
TRDIOA1
PWM2
Counter-phase
TRDIOC1
Normal-phase
TRDGRD1 register
TRDGRB1 register
TRDIOB1
PWM3
Counter-phase
TRDIOD1
NOTE: 1. When bits BFC0, BFD0, BFC1, and BFD1 in the TRDMR register are set to 1 (buffer register).
Figure 14.75
Block Diagram of Reset Synchronous PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 226 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.29
Reset Synchronous PWM Mode Specifications Item Specification f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) The TRD0 register is incremented (the TRD1 register is not used). PWM period : 1/fk x (m+1) Active level width of normal-phase : 1/fk x (m-n) Active level width of counter-phase: 1/fk x (n+1) fk: Frequency of count source m: Value set in the TRDGRA0 register n: Value set in the TRDGRB0 register (PWM1 output), Value set in the TRDGRA1 register (PWM2 output), Value set in the TRDGRB1 register (PWM3 output)
m+1 Normal-phase m-n Counter-phase n+1 (When "L" is selected as the active level)
Count sources
Count operations PWM waveform
Count start condition Count stop conditions
Interrupt request generation timing TRDIOA0 pin function TRDIOB0 pin function TRDIOD0 pin function TRDIOA1 pin function TRDIOC1 pin function TRDIOB1 pin function TRDIOD1 pin function TRDIOC0 pin function INT0 pin function Read from timer Write to timer Select functions
1 (count starts) is written to the TSTART0 bit in the TRDSTR register. * 0 (count stops) is written to the TSTART0 bit in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. The PWM output pin holds output level before the count stops * When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at the compare match in the TRDGRA0 register. The PWM output pin holds level after output change at compare match. * Compare match (the content of the TRD0 register matches content of registers TRDGRj0, TRDGRA1, and TRDGRB1). * The TRD0 register overflows Programmable I/O port or TRDCLK (external clock) input PWM1 output normal-phase output PWM1 output counter-phase output PWM2 output normal-phase output PWM2 output counter-phase output PWM3 output normal-phase output PWM3 output counter-phase output Output inverted every PWM period Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRD0 register. The value can be written to the TRD0 register. * The active level of normal-phase and counter-phase and initial output level selected individually. * Buffer operation (Refer to 14.3.2 Buffer Operation.) * Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output Forced Cutoff.)
j = either A, B, C, or D Rev.3.00 Feb 29, 2008 REJ09B0244-0300 Page 227 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSTR Bit Symbol TSTART0 TSTART1
Address 0137h Bit Name TRD0 count start flag(4) TRD1 count start flag(5)
After Reset 11111100b Function 0 : Count stops (2) 1 : Count starts 0 : Count stops (3) 1 : Count starts
RW RW RW
CSEL0
TRD0 count operation select bit 0 : Count stops at compare match w ith the TRDGRA0 register 1 : Count continues at compare match w ith the TRDGRA0 register TRD1 count operation select bit 0 : Count stops at compare match w ith the TRDGRA1 register 1 : Count continues at compare match w ith the TRDGRA1 register Nothing is assigned. If necessary, set to 0. When read, the content is 1.
RW
CSEL1
RW
-- (b7-b4)
--
NOTES: 1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Register of Notes on Tim er RD. 2. When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit. 3. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit. 4. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 5. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count stops).
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TRDMR Bit Symbol SYNC -- (b3-b1) BFC0 BFD0 BFC1 BFD1
Address 0138h Bit Name Timer RD synchronous bit
After Reset 00001110b Function Set this bit to 0 (registers TRD0 and TRD1 operate independently) in reset synchronous PWM mode.
RW RW
Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select 0 : General register bit 1 : Buffer register of TRDGRA0 register TRDGRD0 register function select 0 : General register bit 1 : Buffer register of TRDGRB0 register TRDGRC1 register function select 0 : General register bit 1 : Buffer register of TRDGRA1 register TRDGRD1 register function select 0 : General register bit 1 : Buffer register of TRDGRB1 register
-- RW RW RW RW
Figure 14.76
Registers TRDSTR and TRDMR in Reset Synchronous PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 228 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol TRDFCR Bit Symbol CMD0 CMD1
Address 013Ah Bit Name Combination mode select bits (1, 2)
After Reset 10000000b Function Set to 01b (reset synchronous PWM mode) in reset synchronous PWM mode.
RW RW RW
OLS0
Normal-phase output level select bit 0 : Initial output "H" (in reset synchronous PWM mode or Active level "L" complementary PWM mode) 1 : Initial output "L" Active level "H" Counter-phase output level select bit 0 : Initial output "H" (in reset synchronous PWM mode or Active level "L" complementary PWM mode) 1 : Initial output "L" Active level "H" A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) External clock input select bit PWM3 mode select bit(3) This bit is disabled in reset synchronous PWM mode. This bit is disabled in reset synchronous PWM mode. 0 : External clock input disabled 1 : External clock input enabled This bit is disabled in reset synchronous PWM mode.
RW
OLS1
RW
ADTRG ADEG STCLK PWM3
RW RW RW RW
NOTES: 1. When bits CMD1 to CMD0 are set to 01b, 10b, or 11b, the MCU enters reset synchronous PWM mode or complementary PWM mode in spite of the setting of the TRDPMR register. 2. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops). 3. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled.
Figure 14.77
TRDFCR Register in Reset Synchronous PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 229 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol TRDOER1 Bit Symbol EA0
Address 013Bh Bit Name TRDIOA0 output disable bit
After Reset FFh Function Set this bit to 1 (the TRDIOA0 pin is used as a programmable I/O port) in reset synchronous PWM mode. 0 : Enable output 1 : Disable output (The TRDIOB0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOC0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOD0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOA1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOB1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOC1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOD1 pin is used as a programmable I/O port.)
RW RW
TRDIOB0 output disable bit EB0 TRDIOC0 output disable bit EC0 TRDIOD0 output disable bit ED0 TRDIOA1 output disable bit EA1 TRDIOB1 output disable bit EB1 TRDIOC1 output disable bit EC1 TRDIOD1 output disable bit ED1
RW
RW
RW
RW
RW
RW
RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 013Ch TRDOER2 Bit Symbol Bit Name -- Nothing is assigned. If necessary, set to 0. (b6-b0) When read, the content is 1.
_____
After Reset 01111111b Function
RW --
PTO
INT0 of pulse output forced 0 : Pulse output forced cutoff input disabled cutoff signal input enabled bit(1) 1 : Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (disable output) w hen "L" is
_____
RW
applied to the INT0 pin.) NOTE: 1. Refer to 14.3.4 Pulse Output Forced Cutoff.
Figure 14.78
Registers TRDOER1 to TRDOER2 in Reset Synchronous PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 230 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Control Register 0(3)
b7 b6 b5 b4 b3 b2 b1 b0
001
Symbol TRDCR0 Bit Symbol TCK0
Address 0140h Bit Name Count source select bits
After Reset 00h Function
b2 b1b0
RW RW
TCK1
TCK2 External clock edge select bits (2) CKEG0
0 0 0 0 1 1 1 1 0 0 1 1
0 0 1 1 0 0 1 1
0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : TRDCLK input(1) 0 : fOCO40M 1 : Do not set.
RW
RW
b4 b3
CKEG1 CCLR0 CCLR1 CCLR2 TRD0 counter clear select bits
0 : Count at the rising edge 1 : Count at the falling edge 0 : Count at both edges 1 : Do not set.
RW
RW RW RW RW
Set to 001b (TRD0 register cleared at compare match w ith TRDGRA0 register) in reset synchronous PWM mode.
NOTES: 1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 3. The TRDCR1 register is not used in reset synchronous PWM mode.
Figure 14.79
TRDCR0 Register in Reset Synchronous PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 231 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSR0 TRDSR1 Bit Symbol
Address 0143h 0153h
After Reset 11100000b 11000000b RW
IMFA
Bit Name Function Input capture/compare match [Source for setting this bit to 0] flag A Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. Input capture/compare match [Source for setting this bit to 0"] flag B Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. Input capture/compare match [Source for setting this bit to 0] flag C Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register (3). Input capture/compare match [Source for setting this bit to 0] flag D Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register (3). Overflow flag [Source for setting this bit to 0] Write 0 after read(2). [Source for setting this bit to 1] When the TRDi register overflow s. This bit is disabled in reset synchronous PWM mode.
RW
IMFB
RW
IMFC
RW
IMFD
RW
OVF
RW
UDF -- (b7-b6)
Underflow flag(1)
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
NOTES: 1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1. 2. The w riting results are as follow s: * This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. * This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0). * This bit remains unchanged if 1 is w ritten to it. 3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.80
Registers TRDSR0 to TRDSR1 in Reset Synchronous PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 232 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDIER0 TRDIER1 Bit Symbol
Address 0144h 0154h Bit Name Input capture/compare match interrupt enable bit A
After Reset 11100000b 11100000b Function 0 : Disable interrupt (IMIA) by the IMFA bit 1 : Enable interrupt (IMIA) by the IMFA bit 0 : Disable interrupt (IMIB) by the IMFB bit 1 : Enable interrupt (IMIB) by the IMFB bit 0 : Disable interrupt (IMIC) by the IMFC bit 1 : Enable interrupt (IMIC) by the IMFC bit 0 : Disable interrupt (IMID) by the IMFD bit 1 : Enable interrupt (IMID) by the IMFD bit RW
IMIEA
RW
IMIEB
Input capture/compare match interrupt enable bit B
RW
IMIEC
Input capture/compare match interrupt enable bit C
RW
IMIED
Input capture/compare match interrupt enable bit D
RW
OVIE
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the bit OVF bit 1 : Enable interrupt (OVI) by the OVF bit Nothing is assigned. If necessary, set to 0. When read, the content is 1.
RW
-- (b7-b5)
--
Figure 14.81
Registers TRDIER0 to TRDIER1 in Reset Synchronous PWM Mode
Timer RD Counter 0(1, 2)
(b15) b7 (b8) b0 b7 b0
Symbol TRD0
Address 0147h-0146h
Function Count a count source. Count operation is incremented. When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. NOTES: 1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. 2. The TRD1 register is not used in reset synchronous PWM mode.
After Reset 0000h Setting Range 0000h to FFFFh
RW RW
Figure 14.82
TRD0 Registrar in Reset Synchronous PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 233 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1
Address 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh Function
After Reset FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW RW
Refer to Table 14.30 TRDGRji Register Functions in Reset Synchronous PWM Mode. NOTE: 1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.83
Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in Reset Synchronous PWM Mode
The following registers are disabled in the reset synchronous PWM mode: TRDPMR, TRDOCR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1. Table 14.30 Register TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 TRDGRC0 TRDGRD0 TRDGRji Register Functions in Reset Synchronous PWM Mode Setting - - BFC0 = 0 BFD0 = 0 - - BFC1 = 0 BFD1 = 0 BFC0 = 1 BFD0 = 1 Register Function General register. Set the PWM period. General register. Set the changing point of PWM1 output. (These registers are not used in reset synchronous PWM mode.) General register. Set the changing point of PWM2 output. General register. Set the changing point of PWM3 output. (These points are not used in reset synchronous PWM mode.) Buffer register. Set the next PWM period. (Refer to 14.3.2 Buffer Operation.) Buffer register. Set the changing point of the next PWM1 output. (Refer to 14.3.2 Buffer Operation.) Buffer register. Set the changing point of the next PWM2 output. (Refer to 14.3.2 Buffer Operation.) Buffer register. Set the changing point of the next PWM3 output. (Refer to 14.3.2 Buffer Operation.) PWM Output Pin (Output inverted every PWM period and TRDIOC0 pin) TRDIOB0 TRDIOD0 - TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 - (Output inversed every PWM period and TRDIOC0 pin) TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1
TRDGRC1
BFC1 = 1
TRDGRD1
BFD1 = 1
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 234 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Count source Value in TRD0 register m
n
p
q 0000h TSTARTi bit in TRDSTR register 1 0 m+1 m-n TRDIOB0 output n+1 TRDIOD0 output
m-p TRDIOA1 output p+1 TRDIOC1 output m-q TRDIOB1 output Initial output "H" q+1 TRDIOD1 output Active level "L" Active level "L"
TRDIOC0 output Initial output "H"
IMFA bit in TRDSR0 register
1 0 Set to 0 by a program Set to 0 by a program
IMFB bit in TRDSR0 register
1 0
IMFA bit in TRDSR1 register
1 0 Set to 0 by a program Set to 0 by a program
IMFB bit in TRDSR1 register
1 0
Transfer from the buffer register to the general register during buffer operation
Transfer from the buffer register to the general register during buffer operation
i = 0 or 1
m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register p: Value set in TRDGRA1 register q: Value set in TRDGRB1 register
The above applies under the following conditions: Bits OLS1 and OLS0 in the TRDFCR register are set to 0 (initial output level "H", active level "L").
Figure 14.84
Operating Example of Reset Synchronous PWM Mode Page 235 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
14. Timers
14.3.9
Complementary PWM Mode
In this mode, 3 normal-phases and 3 counter-phases of the PWM waveform are output with the same period (three-phase, triangular wave modulation, and with dead time). Figure 14.85 shows a Block Diagram of Complementary PWM Mode, and Table 14.31 lists the Complementary PWM Mode Specifications. Figures 14.86 to 14.94 show the Registers Associated with Complementary PWM Mode, Figure 14.95 shows the Output Model of Complementary PWM Mode, and Figure 14.96 shows an Operating Example of Complementary PWM Mode.
Buffer TRDGRA0 register
Waveform control
Period
TRDIOC0
Normal-phase TRDGRD0 register TRDGRC1 register TRDGRD1 register TRDGRB0 register TRDGRA1 register TRDGRB1 register PWM1 Counter-phase Normal-phase PWM2 Counter-phase Normal-phase PWM3 Counter-phase
TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1
Figure 14.85
Block Diagram of Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 236 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.31
Complementary PWM Mode Specifications
Specification f1, f2, f4, f8, f32, fOCO40M External signal input to the TRDCLK pin (valid edge selected by a program) Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count source) as bits TCK2 to TCK0 in the TRDCR0 register. Increment or decrement Registers TRD0 and TRD1 are decremented with the compare match in registers TRD0 and TRDGRA0 during increment operation. The TRD1 register value is changed from 0000h to FFFFh during decrement operation, and registers TRD0 and TRD1 are incremented. PWM period: 1/fk x (m+2-p) x 2(1) Dead time: p Active level width of normal-phase: 1/fk x (m-n-p+1) x 2 Active level width of counter-phase: 1/fk x (n+1-p) x 2 fk: Frequency of count source m: Value set in the TRDGRA0 register n: Value set in the TRDGRB0 register (PWM1 output) Value set in the TRDGRA1 register (PWM2 output) Value set in the TRDGRB1 register (PWM3 output) p: Value set in the TRD0 register
m+2-p n+1 Normal-phase
Item Count sources
Count operations
PWM operations
Counter-phase n+1-p p m-p-n+1 (When "L" is selected as the active level)
Count start condition Count stop conditions
Interrupt request generation timing TRDIOA0 pin function TRDIOB0 pin function TRDIOD0 pin function TRDIOA1 pin function TRDIOC1 pin function TRDIOB1 pin function TRDIOD1 pin function TRDIOC0 pin function INT0 pin function Read from timer Write to timer Select functions
1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register. 0 (count stops) is written to bits TSTART0 and TSTART1 in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. (The PWM output pin holds output level before the count stops.) * Compare match (The content of the TRDi register matches content of the TRDGRji register.) * The TRD1 register underflows Programmable I/O port or TRDCLK (external clock) input PWM1 output normal-phase output PWM1 output counter-phase output PWM2 output normal-phase output PWM2 output counter-phase output PWM3 output normal-phase output PWM3 output counter-phase output Output inverted every 1/2 period of PWM Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input The count value can be read by reading the TRDi register. The value can be written to the TRDi register. * Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output Forced Cutoff.) * The active level of normal-phase and counter-phase and initial output level selected individually * Transfer timing from the buffer register selected * A/D trigger generated
i = 0 or 1, j = either A, B, C, or D NOTE: 1. After a count starts, the PWM period is fixed.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 237 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSTR Bit Symbol TSTART0 TSTART1
Address 0137h Bit Name TRD0 count start flag(4) TRD1 count start flag(5)
After Reset 11111100b Function 0 : Count stops (2) 1 : Count starts 0 : Count stops (3) 1 : Count starts
RW RW RW
CSEL0
TRD0 count operation select bit 0 : Count stops at compare match w ith the TRDGRA0 register 1 : Count continues at compare match w ith the TRDGRA0 register TRD1 count operation select bit 0 : Count stops at compare match w ith the TRDGRA1 register 1 : Count continues at compare match w ith the TRDGRA1 register Nothing is assigned. If necessary, set to 0. When read, the content is 1.
RW
CSEL1
RW
-- (b7-b4)
--
NOTES: 1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Register of Notes on Tim er RD. 2. When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit. 3. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit. 4. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 5. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count stops).
Figure 14.86
TRDSTR Register in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 238 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol TRDMR Bit Symbol
Address 0138h Bit Name Timer RD synchronous bit
SYNC
After Reset 00001110b Function Set this bit to 0 (registers TRD0 and TRD1 operate independently) in complementary PWM mode.
RW
RW
-- (b3-b1) BFC0
Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select bit Set this bit to 0 (general register) in complementary PWM mode. TRDGRD0 register function select bit 0 : General register 1 : Buffer register of TRDGRB0 register TRDGRC1 register function select bit 0 : General register 1 : Buffer register of TRDGRA1 register TRDGRD1 register function select bit 0 : General register 1 : Buffer register of TRDGRB1 register
--
RW
BFD0
RW
BFC1
RW
BFD1
RW
Figure 14.87
TRDMR Register in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 239 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDFCR Bit Symbol
Address 013Ah Bit Name Combination mode select bits (1,2)
After Reset 10000000b Function
b1 b0
RW
CMD0
CMD1
1 0 : Complementary PWM mode (transfer from the buffer register to the general register at the underflow in the TRD1 register) 1 1 : Complementary PWM mode (transfer from the buffer register to the general register at the compare match w ith registers TRD0 and TRDGRA0.) Other than above : Do not set. Normal-phase output level select bit 0 : Initial output "H" Active level "L" (in reset synchronous PWM mode or 1 : Initial output "L" complementary PWM mode) Active level "H" Counter-phase output level select bit 0 : Initial output "H" Active level "L" (in reset synchronous PWM mode or 1 : Initial output "L" complementary PWM mode) Active level "H" A/D trigger enable bit (in complementary PWM mode) A/D trigger edge select bit (in complementary PWM mode) 0 : Disable A/D trigger 1 : Enable A/D trigger (3) 0 : A/D trigger is generated at compare match betw een registers TRD0 and TRDGRA0 1 : A/D trigger is generated at underflow in the TRD1 register 0 : External clock input disabled 1 : External clock input enabled This bit is disabled in complementary PWM mode.
RW
RW
OLS0
RW
OLS1
RW
ADTRG
RW
ADEG
RW
STCLK PWM3
External clock input select bit PWM3 mode select bit(4)
RW RW
NOTES: 1. When setting bits CMD1 to CMD0 to 10b or 11b, the MCU enters complementary PWM mode in spite of the setting of the TRDPMR register. 2. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops). 3. Set the ADCAP bit in the ADC0N0 register to 1 (starts by timer RD). 4. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled.
Figure 14.88
TRDFCR Register in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 240 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol TRDOER1 Bit Symbol
Address 013Bh Bit Name TRDIOA0 output disable bit
EA0
After Reset FFh Function Set this bit to 1 (the TRDIOA0 pin is used as a programmable I/O port) in complementary PWM mode. 0 : Enable output 1 : Disable output (The TRDIOB0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOC0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOD0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOA1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOB1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOC1 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOD1 pin is used as a programmable I/O port.)
RW
RW
TRDIOB0 output disable bit EB0 TRDIOC0 output disable bit EC0 TRDIOD0 output disable bit ED0 TRDIOA1 output disable bit EA1 TRDIOB1 output disable bit EB1 TRDIOC1 output disable bit EC1 TRDIOD1 output disable bit ED1
RW
RW
RW
RW
RW
RW
RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 013Ch TRDOER2 Bit Symbol Bit Name -- Nothing is assigned. If necessary, set to 0. (b6-b0) When read, the content is 1.
_____
After Reset 01111111b Function
RW --
PTO
0 : Pulse output forced cutoff input disabled INT0 of pulse output forced cutoff signal input enabled bit(1) 1 : Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (disable output) w hen "L" is
_____
RW
applied to the INT0 pin.) NOTE: 1. Refer to 14.3.4 Pulse Output Forced Cutoff.
Figure 14.89
Registers TRDOER1 to TRDOER2 in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 241 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Control Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol TRDCR0 TRDCR1 Bit Symbol TCK0
Address 0140h 0150h Bit Name Count source select bits (2)
b2 b1 b0
After Reset 00h 00h Function 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : TRDCLK input(1) 0 : fOCO40M 1 : Do not set. RW RW
TCK1
RW
TCK2 External clock edge select bits (2,3) CKEG0
RW
b4 b3
CKEG1 TRDi counter clear select bits
0 0 1 1
0 : Count at the rising edge 1 : Count at the falling edge 0 : Count at both edges 1 : Do not set.
RW
RW
CCLR0 CCLR1 CCLR2
Set to 000b (disable clearing (free-running operation)) in complementary PWM mode.
RW RW RW
NOTES: 1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 2. Set bits TCK2 to TCK0 and bits CKEG1 to CKEG0 in registers TRDCR0 and TRDCR1 to the same values. 3. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Figure 14.90
Registers TRDCR0 to TRDCR1 in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 242 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSR0 TRDSR1 Bit Symbol
Address 0143h 0153h Bit Name Input capture/compare match flag A
After Reset 11100000b 11000000b Function [Source for setting this bit to 0] Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. [Source for setting this bit to 0] Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. [Source for setting this bit to 0] Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register (3). [Source for setting this bit to 0] Write 0 after read(2). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register (3). [Source for setting this bit to 0] Write 0 after read(2). [Source for setting this bit to 1] When the TRDi register overflow s. [Source for setting this bit to 0] Write 0 after read(2). [Source for setting this bit to 1] When the TRD1 register underflow s. RW
IMFA
RW
Input capture/compare match flag B
IMFB
RW
Input capture/compare match flag C
IMFC
RW
Input capture/compare match flag D
IMFD
RW
Overflow flag OVF
RW
Underflow flag(1) UDF
RW
-- (b7-b6)
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
--
NOTES: 1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1. 2. The w riting results are as follow s: * This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. * This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0). * This bit remains unchanged if 1 is w ritten to it. 3. Including w hen the BFji bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.91
Registers TRDSR0 to TRDSR1 in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 243 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDIER0 TRDIER1 Bit Symbol
Address 0144h 0154h Bit Name Input capture/compare match interrupt enable bit A
After Reset 11100000b 11100000b Function 0 : Disable interrupt (IMIA) by the IMFA bit 1 : Enable interrupt (IMIA) by the IMFA bit 0 : Disable interrupt (IMIB) by the IMFB bit 1 : Enable interrupt (IMIB) by the IMFB bit 0 : Disable interrupt (IMIC) by the IMFC bit 1 : Enable interrupt (IMIC) by the IMFC bit 0 : Disable interrupt (IMID) by the IMFD bit 1 : Enable interrupt (IMID) by the IMFD bit RW
IMIEA
RW
IMIEB
Input capture/compare match interrupt enable bit B
RW
IMIEC
Input capture/compare match interrupt enable bit C
RW
IMIED
Input capture/compare match interrupt enable bit D
RW
OVIE
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the bit OVF and UDF bits 1 : Enable interrupt (OVI) by the OVF and UDF bits Nothing is assigned. If necessary, set to 0. When read, the content is 1.
RW
-- (b7-b5)
--
Figure 14.92
Registers TRDIER0 to TRDIER1 in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 244 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Counter 0(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRD0
Address 0147h-0146h
Function Set the dead time. Count a count source. Count operation is incremented or decremented. When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. NOTE: 1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
After Reset 0000h Setting Range 0000h to FFFFh
RW
RW
Timer RD Counter 1(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRD1
Address 0157h-0156h
Function Select 0000h. Count a count source. Count operation is incremented or decremented. When an underflow occurs, the UDF bit in the TRDSR1 register is set to 1. NOTE: 1. Access the TRD1 register in 16-bit units. Do not access it in 8-bit units.
After Reset 0000h Setting Range 0000h to FFFFh
RW
RW
Figure 14.93
Registers TRD0 to TRD1 in Complementary PWM Mode
Timer RD General Registers Ai, Bi, C1, and Di (i = 0 or 1)(1, 2)
(b15) b7 (b8) b0 b7 b0
Symbol TRDGRA0 TRDGRB0 TRDGRD0 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1
Address 0149h-0148h 014Bh-014Ah 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh
After Reset FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW RW
Function Refer to Table 14.32 TRDGRji Register Functions in Com plem entary PWM Mode. NOTES: 1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units. 2. The TRDGRC0 register is not used in complementary PWM mode.
Figure 14.94
Registers TRDGRAi, TRDGRBi, TRDGRC1, and TRDGRDi in Complementary PWM Mode
The following registers are disabled in the complementary PWM mode: TRDPMR, TRDOCR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1. Rev.3.00 Feb 29, 2008 REJ09B0244-0300 Page 245 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.32
Register TRDGRA0 -
TRDGRji Register Functions in Complementary PWM Mode
Setting Register Function General register. Set the PWM period at initialization. Setting range: Setting value or above in TRD0 register FFFFh - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). General register. Set the changing point of PWM1 output at initialization. Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). General register. Set the changing point of PWM2 output at initialization. Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). General register. Set the changing point of PWM3 output at initialization. Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Do not write to this register when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 (count starts). PWM Output Pin (Output inverted every half period of TRDIOC0 pin)
TRDGRB0
-
TRDIOB0 TRDIOD0
TRDGRA1
-
TRDIOA1 TRDIOC1
TRDGRB1
-
TRDIOB1 TRDIOD1
TRDGRC0 TRDGRD0
- BFD0 = 1
This register is not used in complementary PWM mode.
Buffer register. Set the changing point of next PWM1 output. (Refer to 14.3.2 Buffer Operation.) Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRB0 register for initialization. Buffer register. Set the changing point of next PWM2 output. (Refer to 14.3.2 Buffer Operation.) Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRA1 register for initialization. Buffer register. Set the changing point of next PWM3 output. (Refer to 14.3.2 Buffer Operation.) Setting range: Setting value or above in TRD0 register TRDGRA0 register - TRD0 register setting value or below Set this register to the same value as the TRDGRB1 register for initialization.
- TRDIOB0 TRDIOD0
TRDGRC1
BFC1 = 1
TRDIOA1 TRDIOC1
TRDGRD1
BFD1 = 1
TRDIOB1 TRDIOD1
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register
Since values cannot be written to the TRDGRB0, TRDGRA1, or TRDGRB1 register directly after count operation starts (prohibited item), use the TRDGRD0, TRDGRC1, or TRDGRD1 register as a buffer register. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 246 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Value in TRDi register Value in TRDGRA0 register Value in TRD0 register Value in TRD1 register
Value in TRDGRB0 register
Value in TRDGRA1 register
Value in TRDGRB1 register 0000h
TRDIOB0 output
TRDIOD0 output
TRDIOA1 output
TRDIOC1 output
TRDIOB1 output
TRDIOD1 output
TRDIOC0 output
i = 0 or 1
Figure 14.95
Output Model of Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 247 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Count source Value in TRDi register m+1 m
Value in TRD0 register
n Value in TRD1 register
p
0000h Set to FFFFh Bits TSTART0 and TSTART1 in TRDSTR register 1 0
TRDIOB0 output Initial output "H" Active level "L" TRDIOD0 output
TRDIOC0 output Initial output "H" m+2-p n+1 n+1-p p m-p-n+1 p n+1-p
(m-p-n+1) x 2 Width of normalphase active level UDF bit in TRDSR1 register 1 0 1 0
Dead time
(n+1-p) x 2 Width of counter-phase active level
IMFA bit in TRDSR0 register
Set to 0 by a program
TRDGRB0 register
n Transfer (when bits CMD1 to CMD0 are set to 11b)
n Transfer (when bits CMD1 to CMD0 are set to 10b) Following data Modify with a program
TRDGRD0 register
n
IMFB bit in TRDSR0 register
1 0
Set to 0 by a program
Set to 0 by a program
CMD0, CMD1: Bits in TRDFCR register i = 0 or 1
m: Value set in TRDGRA0 register n: Value set in TRDGRB0 register p: Value set in TRD0 register
The above applies under the following conditions: Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level "H", active level "L" for normal-phase and counter-phase)
Figure 14.96
Operating Example of Complementary PWM Mode Page 248 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
14. Timers
14.3.9.1
Transfer Timing from Buffer Register
* Transfer from the TRDGRD0, TRDGRC1, or TRDGRD1 register to the TRDGRB0, TRDGRA1, or TRDGRB1 register. When bits CMD1 to CMD0 in the TRDFCR register are set to 10b, the content is transferred when the TRD1 register underflows. When bits CMD1 to CMD0 are set to 11b, the content is transferred at compare match between registers TRD0 and TRDGRA0.
14.3.9.2
A/D Trigger Generation
Compare match between registers TRD0 and TRDGRA0 and TRD1 underflow can be used as the conversion start trigger of the A/D converter. The trigger is selected by bits ADEG and ADTRG in the TRDFCR register. Also, set the ADCAP bit in the ADCON0 register to 1 (starts by timer RD).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 249 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.10 PWM3 Mode
In this mode, 2 PWM waveforms are output with the same period. Figure 14.97 shows a Block Diagram of PWM3 Mode, and Table 14.33 lists the PWM3 Mode Specifications. Figures 14.98 to 14.106 show the Registers Associated with PWM3 Mode, and Figure 14.107 shows an Operating Example of PWM3 Mode.
Buffer Compare match signal TRD0 Comparator TRDGRA0 TRDGRC0
TRDIOA0
Output control
Compare match signal Comparator Compare match signal Comparator TRDGRB0 TRDGRD0 TRDGRA1 TRDGRC1
TRDIOB0
Output control
Compare match signal Comparator TRDGRB1 TRDGRD1
Figure 14.97
Block Diagram of PWM3 Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 250 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.33
PWM3 Mode Specifications Specification f1, f2, f4, f8, f32, fOCO40M The TRD0 register is incremented (the TRD1 is not used). PWM period: 1/fk x (m+1) Active level width of TRDIOA0 output: 1/fk x (m-n) Active level width of TRDIOB0 output: 1/fk x (p-q) fk: Frequency of count source m: Value set in the TRDGRA0 register n: Value set in the TRDGRA1 register p: Value set in the TRDGRB0 register q: Value set in the TRDGRB1 register
m+1 n+1 p+1 q+1 TRDIOA0 output m-n TRDIOB0 output p-q (When "H" is selected as the active level)
Item Count sources Count operations PWM waveform
Count start condition Count stop conditions
Interrupt request generation timing TRDIOA0, TRDIOB0 pin functions TRDIOC0, TRDIOD0, TRDIOA1 to TRDIOD1 pin functions INT0 pin function Read from timer Write to timer Select functions
1 (count starts) is written to the TSTART0 bit in the TRDSTR register. * 0 (count stops) is written to the TSTART0 bit in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1. The PWM output pin holds output level before the count stops * When the CSEL0 bit in the TRDSTR register is set to 0, the count stops at the compare match with the TRDGRA0 register. The PWM output pin holds level after output change by compare match. * Compare match (The content of the TRDi register matches content of the TRDGRji register.) * The TRD0 register overflows PWM output Programmable I/O port Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input The count value can be read by reading the TRD0 register. The value can be written to the TRD0 register. * Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse Output Forced Cutoff.) * Buffer Operation (Refer to 14.3.2 Buffer Operation.) * Active level selectable by pin
i = 0 or 1, j = either A, B, C, or D
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 251 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Start Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSTR Bit Symbol TSTART0 TSTART1
Address 0137h Bit Name TRD0 count start flag(4) TRD1 count start flag(5) TRD0 count operation select bit
After Reset 11111100b Function 0 : Count stops (2) 1 : Count starts 0 : Count stops (3) 1 : Count starts 0 : Count stops at compare match w ith the TRDGRA0 register 1 : Count continues at compare match w ith the TRDGRA0 register
RW RW RW
CSEL0
RW
CSEL1
TRD1 count operation select bit 0 : Count stops at compare match w ith [this bit is not used in PWM3 mode] the TRDGRA1 register 1 : Count continues at compare match w ith the TRDGRA1 register Nothing is assigned. If necessary, set to 0. When read, the content is 1.
RW
-- (b7-b4)
--
NOTES: 1. Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 14.3.12.1 TRDSTR Register of Notes on Tim er RD. 2. When the CSEL0 bit is set to 1, w rite 0 to the TSTART0 bit. 3. When the CSEL1 bit is set to 1, w rite 0 to the TSTART1 bit. 4. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count stops). 5. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count stops).
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDMR Bit Symbol SYNC -- (b3-b1) BFC0 BFD0 BFC1 BFD1
Address 0138h Bit Name Timer RD synchronous bit
After Reset 00001110b Function Set this bit to 0 (TRD0 and TRD1 operate independently) in PWM3 mode.
RW RW -- RW RW RW RW
Nothing is assigned. If necessary, set to 0. When read, the content is 1. TRDGRC0 register function select 0 : General register bit 1 : Buffer register of TRDGRA0 register TRDGRD0 register function select 0 : General register bit 1 : Buffer register of TRDGRB0 register TRDGRC1 register function select 0 : General register bit 1 : Buffer register of TRDGRA1 register TRDGRD1 register function select 0 : General register bit 1 : Buffer register of TRDGRB1 register
Figure 14.98
Registers TRDSTR and TRDMR in PWM3 Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 252 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol TRDFCR Bit Symbol CMD0 CMD1
Address 013Ah Bit Name Combination mode select bits (1)
After Reset 10000000b Function Set to 00b (timer mode, PWM mode, or PWM3 mode) in PWM3 mode.
RW RW RW
OLS0
Normal-phase output level select bit (enabled in reset synchronous PWM mode or complementary PWM mode) Counter-phase output level select bit (enabled in reset synchronous PWM mode or complementary PWM mode)
This bit is disabled in PWM3 mode. RW
This bit is disabled in PWM3 mode. RW
OLS1
ADTRG
A/D trigger enable bit This bit is disabled in PWM3 mode. (enabled in complementary PWM mode) A/D trigger edge select bit This bit is disabled in PWM3 mode. (enabled in complementary PWM mode) External clock input select bit PWM3 mode select bit(2) Set this bit to 0 (external clock input disabled) in PWM3 mode. Set this bit to 0 (PWM3 mode) in PWM3 mode.
RW
ADEG
RW
STCLK PWM3
RW RW
NOTES: 1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits are set to 0 (count stops). 2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is enabled.
Figure 14.99
TRDFCR Register in PWM3 Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 253 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Output Master Enable Register 1
b7 b6 b5 b4 b3 b2 b1 b0
111111
Symbol TRDOER1 Bit Symbol EA0
Address 013Bh Bit Name TRDIOA0 output disable bit
After Reset FFh Function 0 : Enable output 1 : Disable output (The TRDIOA0 pin is used as a programmable I/O port.) 0 : Enable output 1 : Disable output (The TRDIOB0 pin is used as a programmable I/O port.) Set these bits to 1 (programmable I/O port) in PWM3 mode.
RW RW
TRDIOB0 output disable bit EB0 EC0 ED0 EA1 EB1 EC1 ED1 TRDIOC0 output disable bit TRDIOD0 output disable bit TRDIOA1 output disable bit TRDIOB1 output disable bit TRDIOC1 output disable bit TRDIOD1 output disable bit
RW RW RW RW RW RW RW
Timer RD Output Master Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 013Ch TRDOER2 Bit Symbol Bit Name -- Nothing is assigned. If necessary, set to 0. (b6-b0) When read, the content is 1.
_____
After Reset 01111111b Function
RW --
PTO
INT0 of pulse output forced cutoff signal input enabled bit(1)
0 : Pulse output forced cutoff input disabled 1 : Pulse output forced cutoff input enabled (All bits in the TRDOER1 register are set to 1 (disable output) w hen "L" is
_____
RW
applied to the INT0 pin.) NOTE: 1. Refer to 14.3.4 Pulse Output Forced Cutoff.
Figure 14.100 Registers TRDOER1 to TRDOER2 in PWM3 Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 254 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Output Control Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDOCR Bit Symbol
Address 013Dh Bit Name TRDIOA0 output level select bit(2)
After Reset 00h Function 0 : Active level "H", initial output "L", output "H" at compare match w ith the TRDGRA1register, output "L" at compare match w ith the TRDGRA0 register 1 : Active level "L", initial output "H", output "L" at compare match w ith the TRDGRA1register, output "H" at compare match w ith the TRDGRA0 register 0 : Active level "H", initial output "L", output "H" at compare match w ith the TRDGRB1register, output "L" at compare match w ith the TRDGRB0 register 1 : Active level "L", initial output "H", output "L" at compare match w ith the TRDGRB1register, output "H" at compare match w ith the TRDGRB0 register These bits are disabled in PWM3 mode.
RW
TOA0
RW
TRDIOB0 output level select bit(2)
TOB0
RW
TOC0 TOD0 TOA1 TOB1 TOC1 TOD1
TRDIOC0 initial output level select bit TRDIOD0 initial output level select bit TRDIOA1 initial output level select bit TRDIOB1 initial output level select bit TRDIOC1 initial output level select bit TRDIOD1 initial output level select bit
RW RW RW RW RW RW
NOTES: 1. Write to the TRDOCR register w hen both bits TSTART0 and TSTART1 in the TRDSTR register are set to 0 (count 2. If the pin function is set for w aveform output (refer to Tables 14.12 and 14.13), the initial output level is output w hen the TRDOCR register is set.
Figure 14.101 TRDOCR Register in PWM3 Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 255 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Control Register 0(2)
b7 b6 b5 b4 b3 b2 b1 b0
001
Symbol TRDCR0 Bit Symbol TCK0
Address 0140h Bit Name Count source select bits
After Reset 00h Function
b2 b1b0
RW RW
TCK1
TCK2 CKEG0 CKEG1 CCLR0 CCLR1 CCLR2
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 : f1 1 : f2 0 : f4 1 : f8 0 : f32 1 : Do not set. 0 : fOCO40M 1 : Do not set.
RW
RW RW RW RW RW RW
External clock edge select bits (1) These bits are disabled in PWM3 mode. TRD0 counter clear select bits Set to 001b (the TRD0 register cleared at compare match w ith TRDGRA0 register) in PWM3 mode.
NOTES: 1. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled). 2. The TRDCR1 register is not used in PWM3 mode.
Figure 14.102 TRDCR0 Register in PWM3 Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 256 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDSR0 TRDSR1 Bit Symbol
Address 0143h 0153h Bit Name Input capture/compare match flag A
IMFA
After Reset 11100000b 11000000b Function [Source for setting this bit to 0] Write 0 after read(1). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRAi register. [Source for setting this bit to 0] Write 0 after read(1). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRBi register. [Source for setting this bit to 0] Write 0 after read(1). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRCi register (2). [Source for setting this bit to 0] Write 0 after read(1). [Source for setting this bit to 1] When the value in the TRDi register matches w ith the value in the TRDGRDi register (2). [Source for setting this bit to 0] Write 0 after read(1). [Source for setting this bit to 1] When the TRDi register overflow s. This bit is disabled in PWM3 mode.
RW
RW
Input capture/compare match flag B
IMFB
RW
Input capture/compare match flag C
IMFC
RW
Input capture/compare match flag D
IMFD
RW
Overflow flag OVF
RW
UDF -- (b7-b6)
Underflow flag(1)
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
NOTES: 1. The w riting results are as follow s: * This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit. * This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit (this bit remains 1 even if it is set to 1 from 0 after reading, and w riting 0). * This bit remains unchanged if 1 is w ritten to it. 2. Including w hen the BFji (j = C or D) bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
Figure 14.103 Registers TRDSR0 to TRDSR1 in PWM3 Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 257 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRDIER0 TRDIER1 Bit Symbol
IMIEA
Address 0144h 0154h Bit Name Input capture/compare match interrupt enable bit A
After Reset 11100000b 11100000b Function 0 : Disable interrupt (IMIA) by the IMFA bit 1 : Enable interrupt (IMIA) by the IMFA bit 0 : Disable interrupt (IMIB) by the IMFB bit 1 : Enable interrupt (IMIB) by the IMFB bit 0 : Disable interrupt (IMIC) by the IMFC bit 1 : Enable interrupt (IMIC) by the IMFC bit 0 : Disable interrupt (IMID) by the IMFD bit 1 : Enable interrupt (IMID) by the IMFD bit
RW
RW
IMIEB
Input capture/compare match interrupt enable bit B
RW
IMIEC
Input capture/compare match interrupt enable bit C
RW
IMIED
Input capture/compare match interrupt enable bit D
RW
OVIE
Overflow /underflow interrupt enable 0 : Disable interrupt (OVI) by the bit OVF bit 1 : Enable interrupt (OVI) by the OVF bit Nothing is assigned. If necessary, set to 0. When read, the content is 1.
RW
-- (b7-b5)
--
Figure 14.104 Registers TRDIER0 to TRDIER1 in PWM3 Mode
Timer RD Counter 0(1, 2)
(b15) b7 (b8) b0 b7 b0
Symbol TRD0
Address 0147h-0146h
Function Count a count source. Count operation is incremented. When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1. NOTES: 1. Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. 2. The TRD1 register is not used in PWM3 mode.
After Reset 0000h Setting Range 0000h to FFFFh
RW RW
Figure 14.105 TRD0 Register in PWM3 Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 258 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RD General Registers Ai, Bi, Ci, and Di (i = 0 or 1)(1)
(b15) b7 (b8) b0 b7 b0
Symbol TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1
Address 0149h-0148h 014Bh-014Ah 014Dh-014Ch 014Fh-014Eh 0159h-0158h 015Bh-015Ah 015Dh-015Ch 015Fh-015Eh
After Reset FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW RW
Function Refer to Table 14.34 TRDGRji Register Functions in PWM3 Mode. NOTE: 1. Access registers TRDGRAi to TRDGRDi in 16-bit units. Do not access them in 8-bit units.
Figure 14.106 Registers TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi in PWM3 Mode The following registers are disabled in the PWM3 mode function: TRDPMR, TRDDF0, TRDDF1, TRDIORA0, TRDIORC0, TRDPOCR0, TRDIORA1, TRDIORC1, and TRDPOCR1.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 259 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.34
TRDGRji Register Functions in PWM3 Mode Register Function General register. Set the PWM period. Setting range: Value set in TRDGRA1 register or above General register. Set the changing point (the active level timing) of PWM output. Setting range: Value set in TRDGRA0 register or below General register. Set the changing point (the timing that returns to initial output level) of PWM output. Setting range: Value set in TRDGRB1 register or above Value set in TRDGRA0 register or below General register. Set the changing point (active level timing) of PWM output. Setting range: Value set in TRDGRB0 register or below BFC0 = 0 (These registers is not used in PWM3 mode.) BFC1 = 0 BFD0 = 0 BFD1 = 0 BFC0 = 1 Buffer register. Set the next PWM period. (Refer to 14.3.2 Buffer Operation.) Setting range: Value set in TRDGRC1 register or above BFC1 = 1 Buffer register. Set the changing point of next PWM output. (Refer to 14.3.2 Buffer Operation.) Setting range: Value set in TRDGRC0 register or below BFD0 = 1 Buffer register. Set the changing point of next PWM output. (Refer to 14.3.2 Buffer Operation.) Setting range: Value set in TRDGRD1 register or above, setting value or below in TRDGRC0 register. BFD1 = 1 Buffer register. Set the changing point of next PWM output. (Refer to 14.3.2 Buffer Operation.) Setting range: Value set in TRDGRD0 register or below PWM Output Pin TRDIOA0
Register Setting TRDGRA0 - TRDGRA1
TRDGRB0
TRDIOB0
TRDGRB1
TRDGRC0 TRDGRC1 TRDGRD0 TRDGRD1 TRDGRC0
-
TRDIOA0
TRDGRC1
TRDGRD0
TRDIOB0
TRDGRD1
BFC0, BFD0, BFC1, BFD1: Bits in TRDMR register Registers TRDGRC0, TRDGRC1, TRDGRD0, and TRDGRD1 are not used in PWM3 mode. To use them as buffer registers, set bits BFC0, BFC1, BFD0, and BFD1 to 0 (general register) and write a value to the TRDGRC0, TRDGRC1, TRDGRD0, or TRDGRD1 register. After this, bits BFC0, BFC1, BFD0, and BFD1 may be set to 1 (buffer register).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 260 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Count source Value in TRD0 register FFFFh m
n
p
q
0000h
TSTART0 bit in TRDSTR register
1 0 Count stop
CSEL0 bit in TRDSTR register
1 0
Set to 0 by a program
m+1 n+1 p+1 q+1 Output "H" at compare match with the TRDGRA1 register Output "L" at compare match with the TRDGRA0 register p-q m-n
TRDIOA0 output
Initial output "L" TRDIOB0 output
IMFA bit in TRDSR0 register
1 0
Set to 0 by a program
Set to 0 by a program
IMFB bit in TRDSR0 register
1 0
Set to 0 by a program
Set to 0 by a program
TRDGRA0 register
m Transfer
m Transfer Following data
TRDGRC0 register
m
Transfer from buffer register to general register
Transfer from buffer register to general register
j = either A or B
m: Value set in TRDGRA0 register n: Value set in TRDGRA1 register p: Value set in TRDGRB0 register q: Value set in TRDGRB1 register
The above applies under the following conditions: * Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 (initial output level "L", output "H" by compare match with the TRDGRj1 register, output "L" at compare match with the TRDGRj0 register). * The BFC0 bit in the TRDMR register is set to 1 (the TRDGRC0 register is used as the buffer register of the TRDGRA0 register).
Figure 14.107 Operating Example of PWM3 Mode Rev.3.00 Feb 29, 2008 REJ09B0244-0300 Page 261 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.11 Timer RD Interrupt
Timer RD generates the timer RD interrupt request based on 6 sources for each channel. The timer RD interrupt has 1 TRDiIC register (bits IR, and ILVL0 to ILVL2), and 1 vector for each channel. Table 14.35 lists the Registers Associated with Timer RD Interrupt, and Figure 14.108 shows a Block Diagram of Timer RD Interrupt. Table 14.35 Registers Associated with Timer RD Interrupt Timer RD Status Register TRDSR0 TRDSR1 Timer RD Interrupt Enable Register TRDIER0 TRDIER1 Timer RD Interrupt Control Register TRD0IC TRD1IC
Channel 0 Channel 1
Channel i
IMFA bit IMIEA bit
IMFB bit IMIEB bit
IMFC bit IMIEC bit
IMFD bit IMIED bit
UDF bit OVF bit
OVIE bit
Timer RD interrupt request (IR bit in TRDiIC register)
i = 0 or 1 IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
Figure 14.108 Block Diagram of Timer RD Interrupt As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit, bits ILVL0 to ILVL2, and IPL. However, since the interrupt source (timer RD interrupt) is generated by a combination of multiple interrupt request sources, the following differences from other maskable interrupts apply: * When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (enable interrupt), the IR bit in the TRDiIC register is set to 1 (interrupt requested). * When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the TRDSRi register, or both of them, are set to 0, the IR bit is set to 0 (interrupt not requested). Therefore, even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be maintained. * When the conditions of other request sources are met, the IR bit remains 1. * When multiple bits in the TRDIERi register are set to 1, which request source causes an interrupt is determined by the TRDSRi register. * Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set each bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions of the registers used in the different modes (Figures 14.40, 14.55, 14.68, 14.80, 14.91, and 14.103).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 262 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Refer to Registers TRDSR0 to TRDSR1 in each mode (Figures 14.40, 14.55, 14.68, 14.80, 14.91, and 14.103) for the TRDSRi register. Refer to Registers TRDIER0 to TRDIER1 in each mode (Figures 14.41, 14.56, 14.69, 14.81, 14.92, and 14.104) for the TRDIERi register. Refer to 12.1.6 Interrupt Control for information on the TRDiIC register and 12.1.5.2 Relocatable Vector Tables for the interrupt vectors.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 263 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.12 Notes on Timer RD 14.3.12.1 TRDSTR Register
* Set the TRDSTR register using the MOV instruction. * When the CSELi (i = 0 to 1) is set to 0 (the count stops at compare match of registers TRDi and TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is written to the TSTARTi bit. * Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the CSELi bit is se to 0. * To stop counting by a program, set the TSTARTi bit after setting the CSELi bit to 1. Although the CSELi bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be stopped. * Table 14.36 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji (j = A, B, C, or D) pin with the timer RD output. Table 14.36 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
TRDIOji Pin Output when Count Stops Hold the output level immediately before the count stops. Hold the output level after output changes by compare match.
Count Stop When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count stops. When the CSELi bit is set to 0, the count stops at compare match of registers TRDi and TRDGRAi.
14.3.12.2 TRDi Register (i = 0 or 1)
* When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to the TRDi register, the value is not written and the TRDi register is set to 0000h. These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi register. - 001b (Clear by the TRDi register at compare match with the TRDGRAi register.) - 010b (Clear by the TRDi register at compare match with the TRDGRBi register.) - 011b (Synchronous clear) - 101b (Clear by the TRDi register at compare match with the TRDGRCi register.) - 110b (Clear by the TRDi register at compare match with the TRDGRDi register.) * When writing the value to the TRDi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV.W #XXXXh, TRD0 ;Writing JMP.B L1 ;JMP.B L1: MOV.W TRD0,DATA ;Reading
14.3.12.3 TRDSRi Register (i = 0 or 1)
When writing the value to the TRDSRi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV.B #XXh, TRDSR0 ;Writing JMP.B L1 ;JMP.B L1: MOV.B TRDSR0,DATA ;Reading
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 264 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.3.12.4 Count Source Switch
* Switch the count source after the count stops. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register. * When changing the count source from fOCO40M to another source and stopping fOCO40M, wait 2 cycles of f1 or more after setting the clock switch, and then stop fOCO40M. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register. (3) Wait 2 or more cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).
14.3.12.5 Input Capture Function
* Set the pulse width of the input capture signal to 3 or more cycles of the timer RD operation clock (refer to Table 14.11 Timer RD Operation Clocks). * The value in the TRDi register is transferred to the TRDGRji register 2 to 3 cycles of the timer RD operation clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or D) (no digital filter).
14.3.12.6 Reset Synchronous PWM Mode
* When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1. * Set to reset synchronous PWM mode by the following procedure: Change procedure (1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode). (4) Set the other registers associated with timer RD again.
14.3.12.7 Complementary PWM Mode
* When complementary PWM mode is used for motor control, make sure OLS0 = OLS1. * Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure. Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer timing from the buffer register to the general register in complementary PWM mode. (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode). (4) Set the registers associated with other timer RD again. Change procedure: When stopping complementary PWM mode (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode). * Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation. When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). The PWM period cannot be changed.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 265 of 485
R8C/24 Group, R8C/25 Group
14. Timers
* If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1, in that order, when changing from increment to decrement operation. When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR register are set to 11b (complementary PWM mode, buffer data transferred at compare match between registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to registers such as the TRDGRA0 register.
Count value in TRD0 register
m+1 Setting value in TRDGRA0 register m
Set to 0 by a program IMFA bit in TRDSR0 register 1 0 Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Not transferred from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 11b (transfer from the buffer register to the general register at compare match of between registers TRD0 and TRDGRA0). No change
Figure 14.109 Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 266 of 485
R8C/24 Group, R8C/25 Group
14. Timers
* The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment operation. The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at underflow in the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this time, the OVF bit remains unchanged.
Count value in TRD0 register
1
0
FFFFh Set to 0 by a program UDF bit in TRDSR0 register OVF bit in TRDSR0 register 1 0 1 0 Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Not transferred from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 10b (transfer from the buffer register to the general register when the TRD1 register underflows). No change
Figure 14.110 Operation when TRD1 Register Underflows in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 267 of 485
R8C/24 Group, R8C/25 Group
14. Timers
* Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register. However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the following cases: Value in buffer register value in TRDGRA0 register: Transfer take place at underflow of the TRD1 register. After this, when the buffer register is set to 0001h or above and a smaller value than the value of the TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0.
n3 m+1 n2 n1 0000h Count value in TRD1 register Count value in TRD0 register
TRDGRD0 register
n2 Transfer
n3 Transfer n2 n3
n2 Transfer n2
n1 Transfer n1
TRDGRB0 register
n1
Transfer with timing set by bits CMD1 to CMD0
Transfer at underflow of TRD1 register because of n3 > m
Transfer at underflow of TRD1 register because of first setting to n2 < m
Transfer with timing set by bits CMD1 to CMD0
TRDIOB0 output
TRDIOD0 output
m: Value set in TRDGRA0 register The above applies under the following conditions: * Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match between registers TRD0 and TRDGRA0 in complementary PWM mode). * Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active `H" for normal-phase and counter-phase).
Figure 14.111 Operation when Value in Buffer Register Value in TRDGRA0 Register in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 268 of 485
R8C/24 Group, R8C/25 Group
14. Timers
When the value in the buffer register is set to 0000h: Transfer takes place at compare match between registers TRD0 and TRDGRA0. After this, when the buffer register is set to 0001h or above and a smaller value than the value of the TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time after setting, the value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0.
m+1 n2 n1 0000h Count value in TRD1 register Count value in TRD0 register
TRDGRD0 register
n1 Transfer
0000h Transfer n1 0000h
n1 Transfer n1 Transfer
TRDGRB0 register
n2
Transfer with timing set by bits CMD1 to CMD0
Transfer at compare match between registers TRD0 and TRDGRA0 because content in TRDGRD0 register is set to 0000h
Transfer at compare match between registers TRD0 and TRDGRA0 because of first setting to 0001h n1 < m
Transfer with timing set by bits CMD1 to CMD0
TRDIOB0 output
TRDIOD0 output
m: Value set in TRDGRA0 register The above applies under the following conditions: * Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of the TRD1 register in PWM mode). * Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active "H" for normal-phase and counter-phase).
Figure 14.112 Operation when Value in Buffer Register Is Set to 0000h in Complementary PWM Mode
14.3.12.8 Count Source fOCO40M
* The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. For supply voltage other than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as the count source).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 269 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.4
Timer RE
Timer RE has the 4-bit counter and 8-bit counter. Timer RE has the following 2 modes: * Real-time clock mode Generate 1-second signal from fC4 and count seconds, minutes, hours, and days of the week. * Output compare mode Count a count source and detect compare matches. The count source for timer RE is the operating clock that regulates the timing of timer operations.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 270 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.4.1
Real-Time Clock Mode
In real-time clock mode, a 1-second signal is generated from fC4 using a divide-by-2 frequency divider, 4-bit counter, and 8-bit counter and used to count seconds, minutes, hours, and days of the week. Figure 14.113 shows a Block Diagram of Real-Time Clock Mode and Table 14.37 lists the Real-Time Clock Mode Specifications. Figures 14.114 to 14.118, and Figures 14.120 and 14.121 show the Registers Associated with Real-Time Clock Mode. Table 14.38 lists the Interrupt Sources, Figure 14.119 shows the Definition of Time Representation and Figure 14.122 shows the Operating Example in Real-Time Clock Mode.
(1/16) fC4 1/2 4-bit counter
(1/256) 8-bit counter (1s) Overflow
Data bus
Overflow
Overflow
Overflow
TRESEC register
TREMIN register
TREHR register
TREWK register 000 PM bit WKIE
H12_H24 bit
DYIE HRIE
Timing control
Timer RE interrupt
MNIE
INT bit
SEIE
BSY bit H12_H24, PM, INT: Bits in TRECR1 register BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 14.113 Block Diagram of Real-Time Clock Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 271 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.37
Real-Time Clock Mode Specifications Specification fC4 Increment 1 (count starts) is written to TSTART bit in TRECR1 register 0 (count stops) is written to TSTART bit in TRECR1 register Select any one of the following: * Update second data * Update minute data * Update hour data * Update day of week data * When day of week data is set to 000b (Sunday) Programmable I/O ports or output of f2, f4, or f8 When reading TRESEC, TREMIN, TREHR, or TREWK register, the count value can be read. The values read from registers TRESEC, TREMIN, and TREHR are represented by the BCD code. When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), the value can be written to registers TRESEC, TREMIN, TREHR, and TREWK. The values written to registers TRESEC, TREMIN, and TREHR are represented by the BCD codes. * 12-hour mode/24-hour mode switch function
Item Count source Count operation Count start condition Count stop condition Interrupt request generation timing
TREO pin function Read from timer
Write to timer
Select function
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 272 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RE Second Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRESEC Bit Symbol SC00 SC01 SC02 SC03 SC10 SC11 SC12
Address 0118h Bit Name 1st digit of second count bits
After Reset 00h Function Setting Range RW RW RW RW RW RW RW RW
Count 0 to 9 every second. When the 0 to 9 digit moves up, 1 is added to the 2nd (BCD digit of second. code) When counting 0 to 5, 60 seconds are counted. 0 to 5 (BCD code)
2nd digit of second count bits
Timer RE busy flag BSY
This bit is set to 1 w hile registers TRESEC, TREMIN, TREHR, and TREWK are updated.
RO
Figure 14.114 TRESEC Register in Real-Time Clock Mode
Timer RE Minute Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TREMIN Bit Symbol MN00 MN01 MN02 MN03 MN10 MN11 MN12
Address 0119h Bit Name 1st digit of minute count bits
After Reset 00h Function Setting Range RW RW RW RW RW RW RW RW
Count 0 to 9 every minute. When the 0 to 9 digit moves up, 1 is added to the 2nd (BCD digit of minute. code) When counting 0 to 5, 60 minutes are 0 to 5 counted. (BCD code) This bit is set to 1 w hile registers TRESEC, TREMIN, TREHR, and TREWK are updated.
2nd digit of minute count bits
Timer RE busy flag BSY
RO
Figure 14.115 TREMIN Register in Real-Time Clock Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 273 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RE Hour Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TREHR Bit Symbol HR00 HR01 HR02 HR03 HR10 HR11 -- (b6) BSY
Address 011Ah Bit Name 1st digit of hour count bits
After Reset 00h Function Setting Range RW RW RW RW RW RW RW --
Count 0 to 9 every hour. When the 0 to 9 digit moves up, 1 is added to the 2nd (BCD digit of hour. code) Count 0 to 1 w hen the H12_H24 bit is 0 to 2 set to 0 (12-hour mode). (BCD Count 0 to 2 w hen the H12_H24 bit is code) set to 1 (24-hour mode).
2nd digit of hour count bits
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RE busy flag This bit is set to 1 w hile registers TRESEC, TREMIN, TREHR, and TREWK are updated.
RO
Figure 14.116 TREHR Register in Real-Time Clock Mode
Timer RE Day of Week Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TREWK Bit Symbol WK0
Address 011Bh Bit Name Day of w eek count bits
After Reset 00h Function
b2 b1 b0
RW RW
WK1
WK2 -- (b6-b3) BSY
0 0 0 : Sunday 0 0 1 : Monday 0 1 0 : Tuesday 0 1 1 : Wednesday 1 0 0 : Thursday 1 0 1 : Friday 1 1 0 : Saturday 1 1 1 : Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Timer RE busy flag This bit is set to 1 w hile registers TRESEC, TREMIN, TREHR, and TREWK are updated.
RW
RW
--
RO
Figure 14.117 TREWK Register in Real-Time Clock Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 274 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RE Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 011Ch TRECR1 Bit Symbol Bit Name -- Nothing is assigned. If necessary, set to 0. (b0) When read, the content is 0. TCSTF TOENA INT Timer RE count status flag TREO pin output enable bit Interrupt request timing bit Timer RE reset bit 0 : Count stopped 1 : Counting
After Reset 00h Function
RW -- RO RW RW
0 : Disable clock output 1 : Enable clock output Set to 1 in real-time clock mode. When setting this bit to 0, after setting it to 1, the follow ings w ill occur. * Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h. * Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0. * The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. When the H12_H24 bit is set to 0 (12-hour mode)(1) 0 : a.m. 1 : p.m. When the H12_H24 bit is set to 1 (24-hour mode), its value is undefined. 0 : 12-hour mode 1 : 24-hour mode 0 : Count stops 1 : Count starts
TRERST
RW
A.m./p.m. bit
PM
RW
H12_H24 TSTART
Operating mode select bit Timer RE count start bit
RW RW
NOTE: 1. This bit is automatically modified w hile timer RE counts.
Figure 14.118 TRECR1 Register in Real-Time Clock Mode
Noon
H12_H24 bit = 1 (24-hour mode) H12_H24 bit = 0 (12-hour mode)
Contents of TREHR Register
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 0
13 1
14 2
15 3
16 4
17 5
Contents of PM bit
Contents in TREWK register
0 (a.m.) 000 (Sunday) Date changes
1 (p.m.)
Contents of TREHR Register
H12_H24 bit = 1 (24-hour mode) H12_H24 bit = 0 (12-hour mode)
18 6
19 7
20 8
21 9
22 10
23 11
0 0
1 1
2 2
3 3

Contents of PM bit
Contents in TREWK register
1 (p.m.) 000 (Sunday)
0 (a.m.) 001 (Monday)
PM bit and H12_H24 bits: Bits in TRECR1 register The above applies to the case when count starts from a.m. 0 on Sunday.
Figure 14.119 Definition of Time Representation Rev.3.00 Feb 29, 2008 REJ09B0244-0300 Page 275 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RE Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TRECR2 Bit Symbol
SEIE
Address 011Dh Bit Name Periodic interrupt triggered every second enable bit(1)
After Reset 00h Function 0 : Disable periodic interrupt triggered every second 1 : Enable periodic interrupt triggered every second 0 : Disable periodic interrupt triggered every minute 1 : Enable periodic interrupt triggered every minute 0 : Disable periodic interrupt triggered every hour 1 : Enable periodic interrupt triggered every hour
RW
RW
MNIE
Periodic interrupt triggered every minute enable bit(1)
RW
HRIE
Periodic interrupt triggered every hour enable bit(1)
RW
DYIE
Periodic interrupt triggered every day 0 : Disable periodic interrupt triggered enable bit(1) every day 1 : Enable periodic interrupt triggered every day Periodic interrupt triggered every w eek enable bit(1) 0 : Disable periodic interrupt triggered every w eek 1 : Enable periodic interrupt triggered every w eek Set to 0 in real-time clock mode.
RW
WKIE
RW
COMIE -- (b7-b6)
Compare match interrupt enable bit
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NOTE: 1. Do not set multiple enable bits to 1 (enable interrupt).
Figure 14.120 TRECR2 Register in Real-Time Clock Mode
Table 14.38
Interrupt Sources Interrupt Source Value in TREWK register is set to 000b (Sunday) (1-week period) TREWK register is updated (1-day period) TREHR register is updated (1-hour period) TREMIN register is updated (1-minute period) TRESEC register is updated (1-second period) Interrupt Enable Bit WKIE DYIE HRIE MNIE SEIE
Factor Periodic interrupt triggered every week Periodic interrupt triggered every day Periodic interrupt triggered every hour Periodic interrupt triggered every minute Periodic interrupt triggered every second
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 276 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RE Count Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
1000
Symbol TRECSR Bit Symbol RCS0 RCS1 RCS2 RCS3 -- (b4) RCS5
Address 011Eh Bit Name Count source select bits
After Reset 00001000b Function Set to 00b in real-time clock mode.
RW RW RW
4-bit counter select bit Real-time clock mode select bit
Set to 0 in real-time clock mode. Set to 1 in real-time clock mode.
RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Clock output select bits (1)
b6 b5
RCS6 -- (b7)
0 0 : f2 0 1 : f4 1 0 : f8 1 1 : Do not set.
RW
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
--
NOTE: 1. Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
Figure 14.121 TRECSR Register in Real-Time Clock Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 277 of 485
R8C/24 Group, R8C/25 Group
14. Timers
1s Approx. 62.5 ms BSY bit Approx. 62.5 ms
Bits SC12 to SC00 in TRESEC register
58
59
00
Bits MN12 to MN00 in TREMIN register
03
04
Bits HR11 to HR00 in TREHR register
(Not changed)
PM bit in TRECR1 register
1 (Not changed) 0
Bits WK2 to WK0 in TREWK register
(Not changed) Set to 0 by acknowledgement of interrupt request or a program
IR bit in TREIC register (when SEIE bit in TRECR2 register is set to 1 (enable periodic interrupt triggered every second)) IR bit in TREIC register (when MNIE bit in TRECR2 register is set to 1 (enable periodic interrupt triggered every minute))
1 0
1 0
BSY: Bit in registers TRESEC, TREMIN, TREHR, and TREWK
Figure 14.122 Operating Example in Real-Time Clock Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 278 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.4.2
Output Compare Mode
In output compare mode, the internal count source divided by 2 is counted using the 4-bit or 8-bit counter and compare value match is detected with the 8-bit counter. Figure 14.123 shows a Block Diagram of Output Compare Mode, and Table 14.39 lists the Output Compare Mode Specifications. Figures 14.124 to 14.128 show the Registers Associated with Output Compare Mode, and Figure 14.129 shows the Operating Example in Output Compare Mode.
f4 f8 RCS1 to RCS0 = 00b = 01b f32 fC4 = 10b = 11b
RCS2 = 0
RCS6 to RCS5 = 00b f2 = 01b = 10b 1/2 4-bit counter
RCS2 = 1
TOENA bit TREO pin
8-bit counter
TQ R
= 11b
Reset TRERST bit Comparison circuit Match signal COMIE bit Timer RE interrupt
TRERST, TOENA: Bits in TRECR1 register COMIE: Bit in TRECR2 register RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register
TRESEC
TREMIN
Data bus
Figure 14.123 Block Diagram of Output Compare Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 279 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Table 14.39
Output Compare Mode Specifications Specification f4, f8, f32, fC4 * Increment * When the 8-bit counter content matches with the TREMIN register content, the value returns to 00h and count continues. The count value is held while count stops. * When RCS2 = 0 (4-bit counter is not used) 1/fi x 2 x (n+1) * When RCS2 = 1 (4-bit counter is used) 1/fi x 32 x (n+1) fi: Frequency of count source n: Setting value of TREMIN register 1 (count starts) is written to the TSTART bit in the TRECR1 register 0 (count stops) is written to the TSTART bit in the TRECR1 register When the 8-bit counter content matches with the TREMIN register content Select any one of the following: * Programmable I/O ports * Output f2, f4, or f8 * Compare output When reading the TRESEC register, the 8-bit counter value can be read. When reading the TREMIN register, the compare value can be read. Writing to the TRESEC register is disabled. When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer stops), writing to the TREMIN register is enabled. * Select use of 4-bit counter * Compare output function Every time the 8-bit counter value matches the TREMIN register value, TREO output polarity is reversed. The TREO pin outputs "L" after reset is deasserted and the timer RE is reset by the TRERST bit in the TRECR1 register. Output level is held by setting the TSTART bit to 0 (count stops).
Item Count sources Count operations
Count period
Count start condition Count stop condition Interrupt request generation timing TREO pin function
Read from timer Write to timer
Select functions
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 280 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RE Counter Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRESEC
Address 0118h Function
After Reset 00h RW RO
8-bit counter data can be read. Although Timer RE stops counting, the count value is held. The TRESEC register is set to 00h at the compare match.
Figure 14.124 TRESEC Register in Output Compare Mode
Timer RE Compare Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TREMIN 8-bit compare data is stored.
Address 0119h Function
After Reset 00h RW RW
Figure 14.125 TREMIN Register in Output Compare Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 281 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RE Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol Address 011Ch TRECR1 Bit Symbol Bit Name Nothing is assigned. If necessary, set to 0. -- When read, the content is 0. (b0) TCSTF TOENA INT Timer RE count status flag TREO pin output enable bit Interrupt request timing bit Timer RE reset bit 0 : Count stopped 1 : Counting
After Reset 00h Function
RW -- RO RW RW
0 : Disable clock output 1 : Enable clock output Set to 0 in output compare mode. When setting this bit to 0, after setting it to 1, the follow ing w ill occur. * Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 are set to 00h. * Bits TCSTF, INT, PM, H12_H24, and TSTART in the TRECR1 register are set to 0. * The 8-bit counter is set to 00h and the 4-bit counter is set to 0h. Set to 0 in output compare mode. 0 : Count stops 1 : Count starts
TRERST
RW
PM H12_H24 TSTART
A.m./p.m. bit Operating mode select bit Timer RE count start bit
RW RW RW
Figure 14.126 TRECR1 Register in Output Compare Mode
Timer RE Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol TRECR2 Bit Symbol SEIE MNIE HRIE DYIE WKIE COMIE -- (b7-b6)
Address 011Dh Bit Name Periodic interrupt triggered every second enable bit Periodic interrupt triggered every minute enable bit Periodic interrupt triggered every hour enable bit Periodic interrupt triggered every day enable bit Periodic interrupt triggered every w eek enable bit Compare match interrupt enable bit
After Reset 00h Function Set to 0 in output compare mode.
RW RW RW RW RW RW
0 : Disable compare match interrupt 1 : Enable compare match interrupt
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Figure 14.127 TRECR2 Register in Output Compare Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 282 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Timer RE Count Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol TRECSR Bit Symbol RCS0
Address 011Eh Bit Name Count source select bits
After Reset 00001000b Function
b1 b0
RW RW
RCS1 4-bit counter select bit
0 0 : f4 0 1 : f8 1 0 : f32 1 1 : fC4
RW
RCS2 RCS3 -- (b4) RCS5
0 : Not used 1 : Used
RW RW --
Real-time clock mode select bit Set to 0 in output compare mode. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Clock output select bits (1)
b6 b5
RCS6 -- (b7)
0 0 : f2 0 1 : f4 1 0 : f8 1 1 : Compare output
RW
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
--
NOTE: 1. Write to bits RCS5 to RCS6 w hen the TOENA bit in the TRECR1 register is set to 0 (disable clock output).
Figure 14.128 TRECSR Register in Output Compare Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 283 of 485
R8C/24 Group, R8C/25 Group
14. Timers
Count starts
8-bit counter content (hexadecimal number)
TREMIN register setting value
Matched
Matched
Matched
00h Set to 1 by a program Time
TSTART bit in TRECR1 register
1 0
2 cycles of maximum count source
TCSTF bit in TRECR1 register
1 0
Set to 0 by acknowledgement of interrupt request or a program
IR bit in TREIC register
1 0
TREO output
1 0
Output polarity is inverted when the compare matches
The above applies under the following conditions. TOENA bit in TRECR1 register = 1 (enable clock output) COMIE bit in TRECR2 register = 1 (enable compare match interrupt) RCS6 to RCS5 bits in TRECSR register = 11b (compare output)
Figure 14.129 Operating Example in Output Compare Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 284 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.4.3
Notes on Timer RE Starting and Stopping Count
14.4.3.1
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. NOTE: 1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and TRECSR.
14.4.3.2
Register Setting
Write to the following registers or bits when timer RE is stopped. * Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 * Bits H12_H24, PM, and INT in TRECR1 register * Bits RCS0 to RCS3 in TRECSR register Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the TRECR2 register. Figure 14.130 shows a Setting Example in Real-Time Clock Mode.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 285 of 485
R8C/24 Group, R8C/25 Group
14. Timers
TSTART in TRECR1 = 0
Stop timer RE operation TCSTF in TRECR1 = 0?
TREIC00h (disable timer RE interrupt)
TRERST in TRECR1 = 1 Timer RE register and control circuit reset TRERST in TRECR1 = 0
Setting of registers TRECSR, TRESEC, TREMIN, TREHR, TREWK, and bits H12_H24, PM, and INT in TRECR1 register
Select clock output Select clock source Seconds, minutes, hours, days of week, operating mode Set a.m./p.m., interrupt timing
Setting of TRECR2
Select interrupt source
Setting of TREIC (IR bit0, select interrupt priority level)
TSTART in TRECR1 = 1 Start timer RE operation TCSTF in TRECR1 = 1?
Figure 14.130 Setting Example in Real-Time Clock Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 286 of 485
R8C/24 Group, R8C/25 Group
14. Timers
14.4.3.3
Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated). Also, when reading several registers, an incorrect time will be read if data is updated before another register is read after reading any register. In order to prevent this, use the reading procedure shown below. * Using an interrupt Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register in the timer RE interrupt routine. * Monitoring with a program 1 Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register is set to 1 (timer RE interrupt request generated). * Monitoring with a program 2 (1) Monitor the BSY bit. (2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY bit is set to 1). (3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the BSY bit is set to 0. * Using read results if they are the same value twice (1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register. (2) Read the same register as (1) and compare the contents. (3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 287 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
15. Serial Interface
The serial interface consists of two channels (UART0 and UART1). Each UARTi (i = 0 or 1) has an exclusive timer to generate the transfer clock and operates independently. Figure 15.1 shows a UARTi (i = 0 or 1) Block Diagram. Figure 15.2 shows a UARTi Transmit/Receive Unit. UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode). Figures 15.3 to 15.6 show the Registers Associated with UARTi.
(UART0)
RXD0 CLK1 to CLK0 = 00b f1 f8 f32
= 01b = 10b
TXD0 1/16
UART reception Clock synchronous type Reception control circuit Receive clock
CKDIR = 0 Internal U0BRG register
1/(n0+1)
External CKDIR = 1
1/16
UART transmission Clock synchronous type Transmission control circuit
Transmit clock
Transmit/ receive unit
Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Clock synchronous type (when internal clock is selected)
1/2
CKDIR = 0 CKDIR = 1
CLK0
CLK polarity switch circuit
TXD1EN
(UART1)
RXD1 CLK1 to CLK0 = 00b f1 f8 f32
= 01b = 10b CKDIR = 0 Internal U1BRG register
TXD1 1/16
UART reception Clock synchronous type Reception control circuit Receive clock
1/(n0+1)
External CKDIR = 1
1/16
UART transmission Clock synchronous type Transmission control circuit
Transmit clock
Transmit/ receive unit
1/2
U1PINSEL
CLK1
CLK polarity switch circuit
Clock synchronous type (when internal clock is selected) Clock synchronous type (when external clock is selected) Clock synchronous type (when internal clock is selected) U1PINSEL
CKDIR = 0 CKDIR = 1
Figure 15.1
UARTi (i = 0 or 1) Block Diagram
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 288 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
1SP
PRYE = 0 Clock PAR disabled synchronous type
Clock synchronous type UART (7 bits) UART (8 bits) UART (7 bits) UARTi receive register
RXDi
SP
2SP
SP
PAR
PAR UART enabled PRYE = 1 UART (9 bits) Clock synchronous type UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0 UiRB register
MSB/LSB conversion circuit Data bus high-order bits Data bus low-order bits MSB/LSB conversion circuit D8 D7
UART (8 bits) UART (9 bits) Clock synchronous type
D6
D5
D4
D3
D2
D1
D0 UiTB register
2SP
PRYE = 1 PAR enabled
UART (9 bits) UART
SP
SP
1SP
PAR
Clock PAR disabled synchronous PRYE = 0 type 0 UART (7 bits) UART (8 bits) Clock synchronous type UART (7 bits) UARTi transmit register i = 0 or 1 SP: Stop bit PAR: Parity bit
TXDi
Figure 15.2
UARTi Transmit/Receive Unit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 289 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
UARTi Transmit Buffer Register (i = 0 or 1)(1, 2)
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB -- (b8-b0) -- (b15-b9) Transmit data
Address 00A3h-00A2h 00ABh-00AAh Function
After Reset Undefined Undefined RW WO --
Nothing is assigned. If necessary, set to 0. When read, the content is undefined.
NOTES: 1. When the transfer data length is 9 bits, w rite data to high byte first, then low byte. 2. Use the MOV instruction to w rite to this register.
UARTi Receive Buffer Register (i = 0 or 1)(1)
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB Bit Symbol -- (b7-b0) -- (b8) -- (b11-b9) OER FER PER SUM
Address 00A7h-00A6h 00AFh-00AEh Bit Name -- --
After Reset Undefined Undefined Function Receive data (D7 to D0) Receive data (D8)
RW RO RO -- RO RO RO RO
Nothing is assigned. If necessary, set to 0. When read, the content is undefined. Overrun error flag(2) Framing error flag(2) Parity error flag(2) Error sum flag(2) 0 : No overrun error 1 : Overrun error 0 : No framing error 1 : Framing error 0 : No parity error 1 : Parity error 0 : No error 1 : Error
NOTES: 1. Read out the UiRB register in 16-bit units. 2. Bits SUM, PER, FER, and OER are set to 0 (no error) w hen bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive disabled). The SUM bit is set to 0 (no error) w hen bits PER, FER, and OER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte of the UiRB register is read out. Also, bits PER and FER are set to 0 w hen reading the high-order byte of the UiRB register.
Figure 15.3
Registers U0TB to U1TB and U0RB to U1RB
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 290 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
UARTi Bit Rate Register (i = 0 or 1)(1, 2, 3)
b7 b0
Address 00A1h 00A9h Function Assuming the set value is n, UiBRG divides the count source by n+1 NOTES: 1. Write to this register w hile the serial I/O is neither transmitting nor receiving. 2. Use the MOV instruction to w rite to this register. 3. After setting the CLK0 to CLK1 bits of the UiC0 register, w rite to the UiBRG register.
Symbol U0BRG U1BRG
After Reset Undefined Undefined Setting Range 00h to FFh
RW WO
UARTi Transmit/Receive Mode Register (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U0MR U1MR Bit Symbol SMD0
Address 00A0h 00A8h Bit Name Serial I/O mode select bits
After Reset 00h 00h Function
b2 b1 b0
RW RW
SMD1
SMD2 CKDIR STPS
0 0 0 : Serial interface disabled 0 0 1 : Clock synchronous serial I/O mode 1 0 0 : UART mode transfer data 7 bits long 1 0 1 : UART mode transfer data 8 bits long 1 1 0 : UART mode transfer data 9 bits long Other than above : Do not set. Internal/external clock select bit 0 : Internal clock 1 : External clock(1) Stop bit length select bit Odd/even parity select bit 0 : 1 stop bit 1 : 2 stop bits Enable w hen PRYE = 1 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled Set to 0.
RW
RW RW RW
PRY Parity enable bit Reserved bit
RW
PRYE -- (b7)
RW RW
NOTE: 1. Set the PD1_6 bit in the PD1 register to 0 (input).
Figure 15.4
Registers U0BRG to U1BRG and U0MR to U1MR
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 291 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
UARTi Transmit/Receive Control Register 0 (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U0C0 U1C0 Bit Symbol CLK0
CLK1 -- (b2) TXEPT -- (b4) NCH
Address 00A4h 00ACh Bit Name BRG count source select b1 b0 0 0 : Selects f1 bits (1) 0 1 : Selects f8 1 0 : Selects f32 1 1 : Do not set. Reserved bit Transmit register empty flag Set to 0.
After Reset 00001000b 00001000b Function
RW RW
RW
RW
0 : Data in transmit register (during transmit) 1 : No data in transmit register (transmit completed)
RO
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Data output select bit CLK polarity select bit 0 : TXDi pin is for CMOS output 1 : TXDi pin is for N-channel open drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
-- RW
CKPOL
RW
UFORM
Transfer format select bit 0 : LSB first 1 : MSB first
RW
NOTE: 1. If the BRG count source is sw itched, set the UiBRG register again.
Figure 15.5
Registers U0C0 to U1C0
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 292 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
UARTi Transmit/Receive Control Register 1 (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0C1 U1C1 Bit Symbol TE TI RE RI UiIRS UiRRM -- (b7-b6)
Address 00A5h 00ADh Bit Name Transmit enable bit(1) Transmit buffer empty flag Receive enable bit Receive complete flag(1) UARTi transmit interrupt cause select bit UARTi continuous receive mode enable bit(2)
After Reset 00000010b 00000010b Function 0 : Disables transmission 1 : Enables transmission 0 : Data in UiTB register 1 : No data in UiTB register 0 : Disables reception 1 : Enables reception 0 : No data in UiRB register 1 : Data in UiRB register 0 : Transmission buffer empty (TI=1) 1 : Transmission completed (TXEPT=1) 0 : Disables continuous receive mode 1 : Enables continuous receive mode
RW RW RO RW RO RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NOTES: 1. The RI bit is set to 0 w hen the higher byte of the UiRB register is read out. 2. Set the UiRRM bit to 0 (disables continuous receive mode) in UART mode.
UART1 Function Select Register
b7 b0
Symbol U1SR
Address 00F5h Function
After Reset Undefined RW
Set to 0Fh w hen using UART1. As a result, UART1 can be used for clock synchronous or clock asynchronous serial I/O. Do not set values other than 0Fh. When read, its content is undefined.
WO
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
00
0000
Symbol Address 00F8h PMR Bit Symbol Bit Name Reserved bits -- (b3-b0) U1PINSEL -- (b6-b5) IICSEL Port CLK1/TXD1/RXD1 sw itch bit Reserved bits SSU / I2C bus sw itch bit
After Reset 00h Function Set to 0. 0 : I/O ports P6_5, P6_6, P6_7 1 : CLK1, TXD1, RXD1 Set to 0. 0 : Selects SSU function 1 : Selects I2C bus function
RW -- RW -- RW
Figure 15.6
Registers U0C1 to U1C1, U1SR, and PMR
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 293 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
15.1
Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock. Table 15.1 lists the Clock Synchronous Serial I/O Mode Specifications. Table 15.2 lists the Registers Used and Settings in Clock Synchronous Serial I/O Mode. Table 15.1 Clock Synchronous Serial I/O Mode Specifications Specification * Transfer data length: 8 bits * CKDIR bit in UiMR register is set to 0 (internal clock): fi/(2(n+1)) fi = f1, f8, f32 n = value set in UiBRG register: 00h to FFh * The CKDIR bit is set to 1 (external clock): input from CLKi pin * Before transmission starts, the following requirements must be met(1) - The TE bit in the UiC1 register is set to 1 (transmission enabled) - The TI bit in the UiC1 register is set to 0 (data in the UiTB register) * Before reception starts, the following requirements must be met(1) - The RE bit in the UiC1 register is set to 1 (reception enabled) - The TE bit in the UiC1 register is set to 1 (transmission enabled) - The TI bit in the UiC1 register is set to 0 (data in the UiTB register) * When transmitting, one of the following conditions can be selected - The UiIRS bit is set to 0 (transmit buffer empty): When transferring data from the UiTB register to UARTi transmit register (when transmission starts). - The UiIRS bit is set to 1 (transmission completes): When completing data transmission from UARTi transmit register. * When receiving When data transfer from the UARTi receive register to the UiRB register (when reception completes). * Overrun error(2) This error occurs if the serial interface starts receiving the next data item before reading the UiRB register and receives the 7th bit of the next data. * CLK polarity selection Transfer data input/output can be selected to occur synchronously with the rising or the falling edge of the transfer clock. * LSB first, MSB first selection Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be selected. * Continuous receive mode selection Receive is enabled immediately by reading the UiRB register.
Item Transfer data format Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request generation timing
Error detection
Select functions
i = 0 or 1 NOTES: 1. If an external clock is selected, ensure that the external clock is "H" when the CKPOL bit in the UiC0 register is set to 0 (transmit data output at falling edge and receive data input at rising edge of transfer clock), and that the external clock is "L" when the CKPOL bit is set to 1 (transmit data output at rising edge and receive data input at falling edge of transfer clock). 2. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 294 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
Table 15.2 Register UiTB UiRB UiBRG UiMR UiC0
Registers Used and Settings in Clock Synchronous Serial I/O Mode(1) Bit 0 to 7 0 to 7 OER 0 to 7 SMD2 to SMD0 CKDIR CLK1 to CLK0 TXEPT NCH CKPOL UFORM TE TI RE RI UiIRS UiRRM Function Set data transmission Data reception can be read Overrun error flag Set bit rate
Set to 001b
UiC1
Select the internal clock or external clock Select the count source in the UiBRG register Transmit register empty flag Select TXDi pin output mode Select the transfer clock polarity Select the LSB first or MSB first Set this bit to 1 to enable transmission/reception Transmit buffer empty flag Set this bit to 1 to enable reception Reception complete flag Select the UARTi transmit interrupt source Set this bit to 1 to use continuous receive mode
i = 0 or 1 NOTE: 1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous serial I/O mode. Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXDi pin outputs "H" level between the operating mode selection of UARTi (i = 0 or 1) and transfer start. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-impedance state.) Table 15.3 Pin Name TXD0 (P1_4) RXD0 (P1_5) I/O Pin Functions in Clock Synchronous Serial I/O Mode Function Output serial data Input serial data Selection Method (Outputs dummy data when performing reception only) PD1_5 bit in PD1 register = 0 (P1_5 can be used as an input port when performing transmission only) CKDIR bit in U0MR register = 0 CKDIR bit in U0MR register = 1 PD1_6 bit in PD1 register = 0 U1PINSEL bit in PMR register = 1 (Outputs dummy data when performing reception only) U1PINSEL bit in PMR register = 1 PD6_7 bit in PD6 register = 0 (P6_7 can be used as an input port when performing transmission only) U1PINSEL bit in PMR register = 1 CKDIR bit in U1MR register = 0 U1PINSEL bit in PMR register = 1 PD6_5 bit in PD6 register = 0 CKDIR bit in U1MR register = 1
CLK0 (P1_6)
Output transfer clock Input transfer clock Output serial data Input serial data
TXD1 (P6_6) RXD1 (P6_7)
CLK1 (P6_5)
Output transfer clock Input transfer clock
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 295 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
* Example of transmit timing (when internal clock is selected)
TC
Transfer clock
TE bit in UiC1 register TI bit in UiC1 register
1 0 1 0
Set data in UiTB register
Transfer from UiTB register to UARTi transmit register TCLK Stop pulsing because the TE bit is set to 0
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TXEPT bit in UiC0 register
1 0
IR bit in SiTIC register
1 0
Set to 0 when interrupt request is acknowledged, or set by a program
TC=TCLK=2(n+1)/fi fi: Frequency of UiBRG count source (f1, f8, f32) The above applies under the following settings: n: Setting value to UiBRG register * CKDIR bit in UiMR register = 0 (internal clock) * CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) * UiIRS bit in UiC1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
* Example of receive timing (when external clock is selected)
RE bit in UiC1 register TE bit in UiC1 register TI bit in UiC1 register 1 0 1 0 1 0
1/fEXT Transfer from UiTB register to UARTi transmit register
Write dummy data to UiTB register
CLKi
Receive data is taken in
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
RI bit in UiC1 register
1 0 1 0
Transfer from UARTi receive register to UiRB register
Read out from UiRB register
IR bit in SiRIC register
Set to 0 when interrupt request is acknowledged, or set by a program
The above applies under the following settings: * CKDIR bit in UiMR register = 1 (external clock) * CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock) The following conditions are met when "H" is applied to the CLKi pin before receiving data: * TE bit in UiC1 register = 1 (enables transmit) * RE bit in UiC1 register = 1 (enables receive) * Write dummy data to the UiTB register fEXT: Frequency of external clock i = 0 or 1
Figure 15.7
Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 296 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
15.1.1
Polarity Select Function
Figure 15.8 shows the Transfer Clock Polarity. Use the CKPOL bit in the UiC0 (i = 0 or 1) register to select the transfer clock polarity.
* When the CKPOL bit in the UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
CLKi(1)
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
* When the CKPOL bit in the UiC0 register = 1 (output transmit data at the rising edge and input receive data at the falling edge of the transfer clock)
CLKi(2) TXDi D0 D1 D2 D3 D4 D5 D6 D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
NOTES: 1. When not transferring, the CLKi pin level is "H". 2. When not transferring, the CLKi pin level is "L". i = 0 or 1
Figure 15.8
Transfer Clock Polarity
15.1.2
LSB First/MSB First Select Function
Figure 15.9 shows the Transfer Format. Use the UFORM bit in the UiC0 (i = 0 or 1) register to select the transfer format.
* When UFORM bit in UiC0 register = 0 (LSB first)(1)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
* When UFORM bit in UiC0 register = 1 (MSB first)(1)
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
NOTE: 1. The above applies when the CKPOL bit in the UiC0 register is set to 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock). i = 0 or 1
Figure 15.9
Transfer Format Page 297 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
15. Serial Interface
15.1.3
Continuous Receive Mode
Continuous receive mode is selected by setting the UiRRM (i = 0 or 1) bit in the UiC1 register to 1 (enables continuous receive mode). In this mode, reading the UiRB register sets the TI bit in the UiC1 register to 0 (data in the UiTB register). When the UiRRM bit is set to 1, do not write dummy data to the UiTB register by a program.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 298 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
15.2
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows data transmission and reception after setting the desired bit rate and transfer data format. Table 15.4 lists the UART Mode Specifications. Table 15.5 lists the Registers Used and Settings for UART Mode. Table 15.4 UART Mode Specifications Specification * Character bit (transfer data): Selectable among 7, 8 or 9 bits * Start bit: 1 bit * Parity bit: Selectable among odd, even, or none * Stop bit: Selectable among 1 or 2 bits * CKDIR bit in UiMR register is set to 0 (internal clock): fj/(16(n+1)) fj = f1, f8, f32 n = value set in UiBRG register: 00h to FFh * CKDIR bit is set to 1 (external clock): fEXT/(16(n+1)) fEXT: Input from CLKi pin, n = value set in UiBRG register: 00h to FFh * Before transmission starts, the following are required - TE bit in UiC1 register is set to 1 (transmission enabled) - TI bit in UiC1 register is set to 0 (data in UiTB register) * Before reception starts, the following are required - RE bit in UiC1 register is set to 1 (reception enabled) - Start bit detected * When transmitting, one of the following conditions can be selected - UiIRS bit is set to 0 (transmit buffer empty): When transferring data from the UiTB register to UARTi transmit register (when transmission starts). - UiIRS bit is set to 1 (transfer ends): When serial interfac.e completes transmitting data from the UARTi transmit register * When receiving When transferring data from the UARTi receive register to UiRB register (when reception ends). * Overrun error(1) This error occurs if the serial interface starts receiving the next data item before reading the UiRB register and receive the bit preceding the final stop bit of the next data item. * Framing error This error occurs when the set number of stop bits is not detected. * Parity error This error occurs when parity is enabled, and the number of 1's in parity and character bits do not match the number of 1's set. * Error sum flag This flag is set is set to 1 when an overrun, framing, or parity error is generated.
Item Transfer data formats
Transfer clocks
Transmit start conditions
Receive start conditions
Interrupt request generation timing
Error detection
i = 0 or 1 NOTE: 1. If an overrun error occurs, the receive data (b0 to b8) of the UiRB register will be undefined. The IR bit in the SiRIC register remains unchanged.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 299 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
Table 15.5 Register UiTB UiRB UiBRG UiMR
Registers Used and Settings for UART Mode Bit 0 to 8 0 to 8 OER,FER,PER,SUM 0 to 7 SMD2 to SMD0 Set transmit data(1) Function Receive data can be read(1, 2) Error flag Set a bit rate Set to 100b when transfer data is 7 bits long Set to 101b when transfer data is 8 bits long Set to 110b when transfer data is 9 bits long Select the internal clock or external clock Select the stop bit Select whether parity is included and whether odd or even Select the count source for the UiBRG register Transmit register empty flag Select TXDi pin output mode Set to 0 LSB first or MSB first can be selected when transfer data is 8 bits long. Set to 0 when transfer data is 7 or 9 bits long. Set to 1 to enable transmit Transmit buffer empty flag Set to 1 to enable receive Receive complete flag Select the source of UARTi transmit interrupt Set to 0
UiC0
CKDIR STPS PRY, PRYE CLK0, CLK1 TXEPT NCH CKPOL UFORM TE TI RE RI UiIRS UiRRM
UiC1
i = 0 or 1 NOTES: 1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long; bits 0 to 7 when transfer data is 8 bits long; bits 0 to 8 when transfer data is 9 bits long. 2. The following bits are undefined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer data is 8 bits long. Table 15.6 lists the I/O Pin Functions in UART Mode. After the UARTi (i = 0 or 1) operating mode is selected, the TXDi pin outputs "H" level. (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a highimpedance state) until transfer starts.) Table 15.6 I/O Pin Functions in UART Mode
Selection Method (Cannot be used as a port when performing reception only) PD1_5 bit in PD1 register = 0 (P1_5 can be used as an input port when performing transmission only) CKDIR bit in U0MR register = 0 CKDIR bit in U0MR register = 1 PD1_6 bit in PD1 register = 0 U1PINSEL bit in PMR register = 1 (Cannot be used as a port when performing reception only) U1PINSEL bit in PMR register = 1 PD6_7 bit in PD6 register = 0 (P6_7 can be used as an input port when performing transmission only) CKDIR bit in U1MR register = 0 U1PINSEL bit in PMR register = 1 PD6_5 bit in PD6 register = 0 CKDIR bit in U1MR register = 1
Pin name Function TXD0 (P1_4) Output serial data RXD0 (P1_5) Input serial data CLK0 (P1_6) Programmable I/O Port Input transfer clock Output serial data
TXD1 (P6_6)
RXD1 (P6_7) Input serial data
CLK1 (P6_5)
Programmable I/O Port Input transfer clock
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 300 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
* Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
TC
Transfer clock
TE bit in UiC1 register TI bit in UiC1 register
1 0 1 0
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register Start bit Parity Stop bit bit
Stop pulsing because the TE bit is set to 0
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
TXEPT bit in UiC0 register
1 0
IR bit SiTIC register
1 0
Set to 0 when interrupt request is acknowledged, or set by a program
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT The above timing diagram applies under the following conditions: * PRYE bit in UiMR register = 1 (parity enabled) fj: Frequency of UiBRG count source (f1, f8, f32) * STPS bit in UiMR register = 0 (1 stop bit) fEXT: Frequency of UiBRG count source (external clock) * UiIRS bit in UiC1 register = 1 (an interrupt request is generated when transmit completes) n: Setting value to UiBRG register i = 0 to 1
* Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
TC
Transfer clock
TE bit in UiC1 register TI bit in UiC1 register
1 0 1 0
Write data to UiTB register
Transfer from UiTB register to UARTi transmit register Start bit Stop Stop bit bit
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP
ST
D0
D1
TXEPT bit in UiC0 register
1 0
IR bit in SiTIC register
1 0 Set to 0 when interrupt request is acknowledged, or set by a program
The above timing diagram applies under the following conditions: * PRYE bit in UiMR register = 0 (parity disabled) * STPS bit in UiMR register = 1 (2 stop bits) * UiIRS bit in UiC1 register = 0 (an interrupt request is generated when transmit buffer is empty)
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT fj: Frequency of UiBRG count source (f1, f8, f32) fEXT: Frequency of UiBRG count source (external clock) n: Setting value to UiBRG register i = 0 to 1
Figure 15.10
Transmit Timing in UART Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 301 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
* Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG output
UiC1 register RE bit RXDi
1 0
Stop bit Start bit D0 D1 D7
Determined to be "L" Receive data taken in Transfer clock Reception triggered when transfer clock is generated by falling edge of start bit UiC1 register RI bit SiRIC register IR bit
1 0 1 0
Transferred from UARTi receive register to UiRB register
Set to 0 when interrupt request is accepted, or set by a program
The above timing diagram applies when the register bits are set as follows: * UiMR register PRYE bit = 0 (parity disabled) * UiMR register STPS bit = 0 (1 stop bit) i = 0 or 1
Figure 15.11
Receive Timing Example in UART Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 302 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
15.2.1
Bit Rate
In UART mode, the bit rate is the frequency divided by the UiBRG (i = 0 or 1) register.
UART mode * Internal clock selected UiBRG register setting value = fj Bit Rate x 16 -1
Fj: Count source frequency of the UiBRG register (f1, f8, or f32)
* External clock selected UiBRG register setting value = fEXT Bit Rate x 16 -1
fEXT: Count source frequency of the UiBRG register (external clock)
i = 0 or 1
Figure 15.12
Calculation Formula of UiBRG (i = 0 or 1) Register Setting Value
Table 15.7
Bit Rate (bps) 1200 2400 4800 9600 14400 19200 28800 38400 57600 115200
Bit Rate Setting Example in UART Mode (Internal Clock Selected)
System Clock = 20 MHz UiBRG Setting Actual Time Setting Error (bps) Value (%) 129 (81h) 1201.92 0.16 64 (40h) 2403.85 0.16 32 (20h) 4734.85 -1.36 129 (81h) 9615.38 0.16 86 (56h) 14367.82 -0.22 64 (40h) 19230.77 0.16 42 (2Ah) 29069.77 0.94 32 (20h) 37878.79 -1.36 21 (15h) 56818.18 -1.36 10 (0Ah) 113636.36 -1.36 System Clock = 18.432 MHz(1) UiBRG Setting Actual Time Setting Error (bps) Value (%) 119 (77h) 1200.00 0.00 59 (3Bh) 2400.00 0.00 29 (1Dh) 4800.00 0.00 119 (77h) 9600.00 0.00 79 (4Fh) 14400.00 0.00 59 (3Bh) 19200.00 0.00 39 (27h) 28800.00 0.00 29 (1Dh) 38400.00 0.00 19 (13h) 57600.00 0.00 9 (09h) 115200.00 0.00 System Clock = 8 MHz UiBRG Setting Value 51 (33h) 25 (19h) 12 (0Ch) 51 (33h) 34 (22h) 25 (19h) 16 (10h) 12 (0Ch) 8 (08h) - Actual Setting Time Error (bps) (%) 1201.92 0.16 2403.85 0.16 4807.69 0.16 9615.38 0.16 14285.71 -0.79 19230.77 0.16 29411.76 2.12 38461.54 0.16 55555.56 -3.55 - -
UiBRG Count Source f8 f8 f8 f1 f1 f1 f1 f1 f1 f1
i = 0 or 1 NOTE: 1. For the high-speed on-chip oscillator, the correction value in the FRA7 register should be written into the FRA1 register. This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20 in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator, refer to 20. Electrical Characteristics.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 303 of 485
R8C/24 Group, R8C/25 Group
15. Serial Interface
15.3
Notes on Serial Interface
* When reading data from the UiRB (i = 0 or 1) register either in the clock synchronous serial I/O mode or in the clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0. To check receive errors, read the UiRB register and then use the read data. Example (when reading receive buffer register): MOV.W 00A6H,R0 ; Read the U0RB register * When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data length, write data to the high-order byte first then the low-order byte, in 8-bit units. Example (when reading transmit buffer register): MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 304 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16. Clock Synchronous Serial Interface
The clock synchronous serial interface is configured as follows. Clock synchronous serial interface Clock synchronous serial I/O with chip select (SSU) Clock synchronous communication mode 4-wire bus communication mode I2C bus Interface I2C bus interface mode Clock synchronous serial mode The clock synchronous serial interface uses the registers at addresses 00B8h to 00BFh. Registers, bits, symbols, and functions vary even for the same addresses depending on the mode. Refer to the register diagrams of each function for details. Also, the differences between clock synchronous communication mode and clock synchronous serial mode are the options of the transfer clock, clock output format, and data output format.
16.1
Mode Selection
The clock synchronous serial interface has four modes. Table 16.1lists the Mode Selections. Refer to 16.2 Clock Synchronous Serial I/O with Chip Select (SSU) and the sections that follow for details of each mode. Table 16.1
IICSEL Bit in PMR Register 0 0 1 1
Mode Selections
Bit 0 in 00BDh Bit 7 in 00B8h (SSUMS Bit in SSMR2 (ICE Bit in ICCR1 Function Register, FS Bit in Register) SAR Register) 0 0 Clock synchronous serial I/O with chip select 0 1 1 0 I2C bus interface 1 1 Mode Clock synchronous communication mode 4-wire bus communication mode I2C bus interface mode Clock synchronous serial mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 305 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2
Clock Synchronous Serial I/O with Chip Select (SSU)
Clock synchronous serial I/O with chip select supports clock synchronous serial data communication. Table 16.2 lists the Clock Synchronous Serial I/O with Chip Select Specifications, and Figure 16.1 shows a Block Diagram of Clock Synchronous Serial I/O with Chip Select. Figures 16.2 to 16.9 show Clock Synchronous Serial I/O with Chip Select Associated Registers. Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications Specification
* Transfer data length: 8 bits Continuous transmission and reception of serial data are supported since both transmitter and receiver have buffer structures. Operating modes * Clock synchronous communication mode * 4-wire bus communication mode (including bidirectional communication) Master/slave device Selectable I/O pins SSCK (I/O): Clock I/O pin SSI (I/O): Data I/O pin SSO (I/O): Data I/O pin SCS (I/O): Chip-select I/O pin Transfer clocks * When the MSS bit in the SSCRH register is set to 0 (operates as slave device), external clock is selected (input from SSCK pin). * When the MSS bit in the SSCRH register is set to 1 (operates as master device), internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16, f1/8 and f1/4, output from SSCK pin) is selected. * Clock polarity and phase of SSCK can be selected. Receive error detection * Overrun error Overrun error occurs during reception and completes in error. While the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and when next serial data receive is completed, the ORER bit is set to 1. Multimaster error * Conflict error When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus detection communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device) and when starting a serial communication, the CE bit in the SSSR register is set to 1 if "L" applies to the SCS pin input. When the SSUMS bit in the SSMR2 register is set to 1 (4-wire bus communication mode), the MSS bit in the SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes state from "L" to "H", the CE bit in the SSSR register is set to 1. Interrupt requests 5 interrupt requests (transmit-end, transmit-data-empty, receive-data-full, overrun error, and conflict error).(1) Select functions * Data transfer direction Selects MSB-first or LSB-first * SSCK clock polarity Selects "L" or "H" level when clock stops * SSCK clock phase Selects edge of data change and data download NOTE: 1. Clock synchronous serial I/O with chip select has only one interrupt vector table.
Item Transfer data format
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 306 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
f1
Internal clock (f1/i)
Internal clock generation circuit
Multiplexer SSCK SSMR register SSCRL register SSCRH register SCS Transmit/receive control circuit SSER register SSSR register SSMR2 register SSTDR register
Data bus
SSO Selector SSI
SSTRSR register
SSRDR register
Interrupt requests (TXI, TEI, RXI, OEI, and CEI) i = 4, 8, 16, 32, 64, 128, or 256
Figure 16.1
Block Diagram of Clock Synchronous Serial I/O with Chip Select
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 307 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SS Control Register H
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSCRH Bit Symbol CKS0
Address 00B8h Bit Name Transfer clock rate select bits (1)
After Reset 00h Function
b2 b1 b0
RW RW
CKS1
CKS2 -- (b4-b3) MSS
0 0 0 : f1/256 0 0 1 : f1/128 0 1 0 : f1/64 0 1 1 : f1/32 1 0 0 : f1/16 1 0 1 : f1/8 1 1 0 : f1/4 1 1 1 : Do not set. Nothing is assigned. If necessary, set to 0. When read, the content is 0. Master/slave device select bit Receive single stop bit
(3) (2)
RW
RW
-- RW
0 : Operates as slave device 1 : Operates as master device 0 : Maintains receive operation after receiving 1 byte of data 1 : Completes receive operation after receiving 1 byte of data
RSSTP
RW
-- (b7)
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
--
NOTES: 1. The set clock is used w hen the internal clock is selected. 2. The SSCK pin functions as the transfer clock output pin w hen the MSS bit is set to 1 (operates as master device). The MSS bit is set to 0 (operates as slave device) w hen the CE bit in the SSSR register is set to 1 (conflict error occurs). 3. The RSSTP bit is disabled w hen the MSS bit is set to 0 (operates as slave device).
Figure 16.2
SSCRH Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 308 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SS Control Register L
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 00B9h SSCRL Bit Symbol Bit Name -- Nothing is assigned. If necessary, set to 0. (b0) When read, the content is 1. Clock synchronous serial I/O w ith chip select control part reset bit
After Reset 01111101b Function RW --
SRES
When this bit is set to 1, the clock synchronous serial I/O w ith chip select control block and SSTRSR register are reset. The values of the registers (1) in the clock synchronous serial I/O w ith chip select register are maintained.
RW
-- (b3-b2)
Nothing is assigned. If necessary, set to 0. When read, the content is 1. SOL w rite protect bit(2) The output level can be changed by the SOL bit w hen this bit is set to 0. The SOLP bit remains unchanged even if 1 is w ritten to it. When read, the content is 1. Serial data output value When read setting bit 0 : The serial data output is set to "L". 1 : The serial data output is set to "H". When w ritten(2,3) 0 : The data output is "L" after the serial data output. 1 : The data output is "H" after the serial data output.
--
SOLP
RW
SOL
RW
-- (b6) -- (b7)
Nothing is assigned. If necessary, set to 0. When read, the content is 1. Nothing is assigned. If necessary, set to 0. When read, the content is 0.
-- --
NOTES: 1. Registers SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR, and SSRDR. 2. The data output after serial data is output can be changed by w riting to the SOL bit before or after transfer. When w riting to the SOL bit, set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction. 3. Do not w rite to the SOL bit during data transfer.
Figure 16.3
SSCRL Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 309 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SS Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol SSMR Bit Symbol BC0
Address 00BAh Bit Name Bits counter 2 to 0
After Reset 00011000b Function
b2 b1 b0
RW RO
BC1
BC2 -- (b3) -- (b4) Reserved bit
0 0 0 : 8 bits left 0 0 1 : 1 bit left 0 1 0 : 2 bits left 0 1 1 : 3 bits left 1 0 0 : 4 bits left 1 0 1 : 5 bits left 1 1 0 : 6 bits left 1 1 1 : 7 bits left Set to 1. When read, the content is 1.
RO
RO
RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 1. SSCK clock phase select bit
(1)
CPHS
0 : Change data at odd edge (Dow nload data at even edge) 1 : Change data at even edge (Dow nload data at odd edge) 0 : "H" w hen clock stops 1 : "L" w hen clock stops 0 : Transfers data MSB first 1 : Transfers data LSB first
RW
CPOS MLS
SSCK clock polarity select bit(1) MSB first/LSB first select bit
RW RW
NOTE: 1. Refer to 16.2.1.1 Association betw een Transfer Clock Polarity, Phase, and Data for the settings of the CPHS and CPOS bits.
Figure 16.4
SSMR Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 310 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SS Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSER Bit Symbol
CEIE
Address After Reset 00BBh 00h Bit Name Function Conflict error interrupt enable bit 0 : Disables conflict error interrupt request 1 : Enables conflict error interrupt request
RW
RW
-- (b2-b1) RE TE
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Receive enable bit Transmit enable bit Receive interrupt enable bit 0 : Disables receive 1 : Enables receive 0 : Disables transmit 1 : Enables transmit 0 : Disables receive data full and overrun error interrupt request 1 : Enables receive data full and overrun error interrupt request
-- RW RW
RIE
RW
TEIE
Transmit end interrupt enable bit 0 : Disables transmit end interrupt request 1 : Enables transmit end interrupt request Transmit interrupt enable bit 0 : Disables transmit data empty interrupt request 1 : Enables transmit data empty interrupt request
RW
TIE
RW
Figure 16.5
SSER Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 311 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SS Status Register(7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSSR Bit Symbol CE -- (b1) ORER -- (b4-b3) RDRF
Address 00BCh Bit Name Conflict error flag(1)
After Reset 00h Function 0 : No conflict errors generated 1 : Conflict errors generated(2)
RW RW -- RW -- RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Overrun error flag
(1)
0 : No overrun errors generated 1 : Overrun errors generated(3)
Nothing is assigned. If necessary, set to 0. When read, the content is 0. Receive data register full
(1,4)
0 : No data in SSRDR register 1 : Data in SSRDR register 0 : The TDRE bit is set to 0 w hen transmitting the last bit of transmit data 1 : The TDRE bit is set to 1 w hen transmitting the last bit of transmit data 0 : Data is not transferred from registers SSTDR to SSTRSR 1 : Data is transferred from registers SSTDR to SSTRSR
Transmit end TEND
(1, 5)
RW
Transmit data empty (1, 5, 6) TDRE
RW
NOTES: 1. Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits invalid. To set any of these bits to 0, first read 1 then w rite 0. 2. When the serial communication is started w hile the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit is set
_____ _____
3.
4. 5. 6. 7.
to 1 if "L" is applied to the SCS pin input. Refer to 16.2.7 SCS Pin Control and Arbitration for more information. When the SSUMS bit in the SSMR2 register is set to 1 (four-w ire bus communication mode), the MSS bit in the _____ SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes the level from "L" to "H" during transfer, the CE bit is set to 1. Indicates w hen overrun errors occur and receive completes by error reception. If the next serial data receive operation is completed w hile the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1. After the ORER bit is set to 1 (overrun error), transmit and receive operations are disabled w hile the bit remains 1. The RDRF bit is set to 0 w hen reading out the data from the SSRDR register. Bits TEND and TDRE are set to 0 w hen w riting data to the SSTDR register. The TDRE bit is set to 1 w hen the TE bit in the SSER register is set to 1 (transmit enabled). When accessing the SSSR register continuously, insert one or more NOP instructions betw een the instructions to access it.
Figure 16.6
SSSR Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 312 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SS Mode Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSMR2 Bit Symbol SSUMS CSOS SOOS SCKOS
Address After Reset 00BDh 00h Bit Name Function Clock synchronous serial I/O w ith 0 : Clock synchronous communication mode chip select mode select bit(1) 1 : Four-w ire bus communication mode
_____
RW RW RW RW RW
SCS pin open drain output select bit Serial data pin open output drain select bit(1) SSCK pin open drain output select bit SCS pin select bits (2)
_____
0 : CMOS output 1 : N-channel open drain output 0 : CMOS output(5) 1 : N-channel open drain output 0 : CMOS output 1 : N-channel open drain output
b5 b4
CSS0
CSS1 SCKS SSCK pin select bit Bidirectional mode enable bit BIDE
(1, 4)
0 0 : Functions 0 1 : Functions 1 0 : Functions 1 1 : Functions
as as as as
port _____ SCS input pin _____ SCS output pin(3) _____ SCS output pin(3)
RW
RW RW
0 : Functions as port 1 : Functions as serial clock pin 0 : Standard mode (communication using 2 pins of data input and data output) 1 : Bidirectional mode (communication using 1 pin of data input and data output)
RW
NOTES: 1. Refer to 16.2.2.1 Association betw een Data I/O Pins and SS Shift Register for information on combinations of data I/O pins.
_____
2. The SCS pin functions as a port, regardless of the values of bits CSS0 and CSS1 w hen the SSUMS bit is set to 0 (clock synchronous communication mode). 3. This bit functions as the SCS input pin before starting transfer. 4. The BIDE bit is disabled w hen the SSUMS bit is set to 0 (clock synchronous communication mode). 5. The SSI pin and SSO pin corresponding port direction bits are set to 0 (input mode) w hen the SOOS bit is set to 0 (CMOS output).
Figure 16.7
SSMR2 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 313 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SS Transmit Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSTDR
Address 00BEh
After Reset FFh
Function RW Store the transmit data. The stored transmit data is transferred to the SSTRSR register and transmission is started w hen it is detected that the SSTRSR register is empty. When the next transmit data is w ritten to the SSTDR register during the data transmission from RW the SSTRSR register, the data can be transmitted continuously. When the MLS bit in the SSMR register is set to 1 (transfer data w ith LSB-first), the data in w hich MSB and LSB are reversed is read, after w riting to the SSTDR register.
SS Receive Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SSRDR
Address 00BFh
After Reset FFh RW
Function Store the receive data.(1) The receive data is transferred to the SSRDR register and the receive operation is completed w hen 1 byte of data has been received by the SSTRSR register. At this time, the next receive operation is possible. Continuous reception is possible using registers SSTRSR and SSRDR.
RO
NOTE: 1. The SSRDR register retains the data received before an overrun error occurs (ORER bit in the SSSR register set to 1 (overrun error)). When an overrun error occurs, the receive data may contain errors and therefore should be discarded.
Figure 16.8
Registers SSTDR and SSRDR
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
00
0000
Symbol Address 00F8h PMR Bit Symbol Bit Name Reserved bits -- (b3-b0) U1PINSEL -- (b6-b5) IICSEL Port CLK1/TXD1/RXD1 sw itch bit Reserved bits SSU / I2C bus sw itch bit
After Reset 00h Function Set to 0. 0 : I/O ports P6_5, P6_6, P6_7 1 : CLK1, TXD1, RXD1 Set to 0. 0 : Selects SSU function 1 : Selects I2C bus function
RW -- RW -- RW
Figure 16.9
PMR Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 314 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.1
Transfer Clock
The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8, and f1/4) and an external clock. When using clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and select the SSCK pin as the serial clock pin. When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the transfer rate selected by bits CKS0 to CKS2 in the SSCRH register. When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected and the SSCK pin functions as input.
16.2.1.1
Association between Transfer Clock Polarity, Phase, and Data
The association between the transfer clock polarity, phase and data changes according to the combination of the SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register. Figure 16.10 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data. Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register. When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is set to 0, transfer is started from the MSB and proceeds to the LSB.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 315 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
* SSUMS = 0 (clock synchronous communication mode), CPHS bit = 0 (data change at odd edge), and CPOS bit = 0 ("H" when clock stops)
SSCK
SSO, SSI
b0
b1
b2
b3
b4
b5
b6
b7
* SSUMS = 1 (4-wire bus communication mode) and CPHS = 0 (data change at odd edge)
SSCK CPOS = 0 ("H" when clock stops) SSCK CPOS = 1 ("L" when clock stops) SSO, SSI b0 b1 b2 b3 b4 b5 b6 b7
SCS
* SSUMS = 1 (4-wire bus communication mode) and CPHS = 1 (data download at odd edge)
SSCK CPOS = 0 ("H" when clock stops) SSCK CPOS = 1 ("L" when clock stops) SSO, SSI b0 b1 b2 b3 b4 b5 b6 b7
SCS CPHS and CPOS: Bits in SSMR register, SSUMS: Bits in SSMR2 register
Figure 16.10
Association between Transfer Clock Polarity, Phase, and Transfer Data
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 316 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.2
SS Shift Register (SSTRSR)
The SSTRSR register is a shift register for transmitting and receiving serial data. When transmit data is transferred from the SSTDR register to the SSTRSR register and the MLS bit in the SSMR register is set to 0 (MSB-first), the bit 0 in the SSTDR register is transferred to bit 0 in the SSTRSR register. When the MLS bit is set to 1 (LSB-first), bit 7 in the SSTDR register is transferred to bit 0 in the SSTRSR register.
16.2.2.1
Association between Data I/O Pins and SS Shift Register
The connection between the data I/O pins and SSTRSR register (SS shift register) changes according to a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register. The connection also changes according to the BIDE bit in the SSMR2 register. Figure 16.11 shows the Association between Data I/O Pins and SSTRSR Register.
* SSUMS = 0 (clock synchronous communication mode)
* SSUMS = 1 (4-wire bus communication mode), BIDE = 0 (standard mode), and MSS = 1 (operates as master device)
SSTRSR register
SSO
SSTRSR register
SSO
SSI
SSI
* SSUMS = 1 (4-wire bus communication mode), BIDE = 0 (standard mode), and MSS = 0 (operates as slave device)
* SSUMS = 1 (4-wire bus communication mode) and BIDE = 1 (bidirectional mode)
SSTRSR register
SSO
SSTRSR register
SSO
SSI
SSI
Figure 16.11
Association between Data I/O Pins and SSTRSR Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 317 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.3
Interrupt Requests
Clock synchronous serial I/O with chip select has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the clock synchronous serial I/O with chip select interrupt vector table, determining interrupt sources by flags is required. Table 16.3 shows the Clock Synchronous Serial I/O with Chip Select Interrupt Requests. Table 16.3 Clock Synchronous Serial I/O with Chip Select Interrupt Requests Abbreviation TXI TEI RXI OEI CEI Generation Condition TIE = 1, TDRE = 1 TEIE = 1, TEND = 1 RIE = 1, RDRF = 1 RIE = 1, ORER = 1 CEIE = 1, CE = 1
Interrupt Request Transmit data empty Transmit end Receive data full Overrun error Conflict error
CEIE, RIE, TEIE and TIE: Bits in SSER register ORER, RDRF, TEND and TDRE: Bits in SSSR register If the generation conditions in Table 16.3 are met, a clock synchronous serial I/O with chip select interrupt request is generated. Set each interrupt source to 0 by a clock synchronous serial I/O with chip select interrupt routine. However, the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data transmitted from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register. Setting the TDRE bit to 0 (data not transmitted from registers SSTDR to SSTRSR) can cause an additional byte of data to be transmitted.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 318 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.4
Communication Modes and Pin Functions
Clock synchronous serial I/O with chip select switches the functions of the I/O pins in each communication mode according to the setting of the MSS bit in the SSCRH register and bits RE and TE in the SSER register. Table 16.4 shows the Association between Communication Modes and I/O Pins. Table 16.4 Association between Communication Modes and I/O Pins Bit Setting SSUMS BIDE MSS TE 0 Disabled 0 0 1 1 0 1 4-wire bus communication mode 1 0 0 0 1 1 0 1 4-wire bus 1 (bidirectional) communication mode(2) 1 0 1 0 1 0 1 RE 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 SSI Input -(1) Input Input -(1) Input -(1) Output Output Input -(1) Input -(1) -(1) -(1) -(1) Pin State SSO -(1) Output Output -(1) Output Output Input -(1) Input -(1) Output Output Input Output Input Output SSCK Input Input Input Output Output Output Input Input Input Output Output Output Input Input Output Output
Communication Mode Clock synchronous communication mode
NOTES: 1. This pin can be used as a programmable I/O port. 2. Do not set both bits TE and RE to 1 in 4-wire bus (bidirectional) communication mode. SSUMS and BIDE: Bits in SSMR2 register MSS: Bit in SSCRH register TE and RE: Bits in SSER register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 319 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.5
Clock Synchronous Communication Mode Initialization in Clock Synchronous Communication Mode
16.2.5.1
Figure 16.12 shows Initialization in Clock Synchronous Communication Mode. To initialize, set the TE bit in the SSER register to 0 (transmit disabled) and the RE bit to 0 (receive disabled) before data transmission or reception. Set the TE bit to 0 and the RE bit to 0 before changing the communication mode or format. Setting the RE bit to 0 does not change the contents of flags RDRF and ORER or the contents of the SSRDR register.
Start
SSER register
RE bit 0 TE bit 0 SSUMS bit 0
SSMR2 register
SSMR register
CPHS bit 0 CPOS bit 0 Set MLS bit
SSCRH register
Set MSS bit
SSMR2 register
SCKS bit 1 Set SOOS bit
SSCRH register
Set bits CKS0 to CKS2 Set RSSTP bit ORER bit 0(1)
SSSR register
SSER register
RE bit 1 (receive) TE bit 1 (transmit) Set bits RIE, TEIE, and TIE
End NOTE: 1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 16.12
Initialization in Clock Synchronous Communication Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 320 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.5.2
Data Transmission
Figure 16.13 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Transmission (Clock Synchronous Communication Mode). During data transmission, the clock synchronous serial I/O with chip select operates as described below. When clock synchronous serial I/O with chip select is set as a master device, it outputs a synchronous clock and data. When clock synchronous serial I/O with chip select is set as a slave device, it outputs data synchronized with the input clock. When the TE bit is set to 1 (transmit enabled) before writing the transmit data to the SSTDR register, the TDRE bit is automatically set to 0 (data not transferred from registers SSTDR to SSTRSR) and the data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data transferred from registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1, the TXI interrupt request is generated. When one frame of data is transferred while the TDRE bit is set to 0, data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while the TDRE bit is set to 1, the TEND bit in the SSSR register is set to 1 (the TDRE bit is set to 1 when the last bit of the transmit data is transmitted) and the state is retained. The TEI interrupt request is generated when the TEIE bit in the SSER register is set to 1 (transmit-end interrupt request enabled). The SSCK pin is fixed "H" after transmit-end. Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm that the ORER bit is set to 0 before transmission. Figure 16.14 shows a Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode).
* SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data change at odd numbers), and CPOS = 0 ("H" when clock stops)
SSCK
SSO
b0
b1
b7
b0
b1
b7
1 frame TDRE bit in SSSR register 1 0 1 0 TXI interrupt request generation
1 frame TEI interrupt request generation
TEND bit in SSSR register
Processing by program
Write data to SSTDR register
Figure 16.13
Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Transmission (Clock Synchronous Communication Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 321 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE = 1 ? Yes
No
(1) After reading the SSSR register and confirming that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When the transmit data is written to the SSTDR register, the TDRE bit is automatically set to 0.
Write transmit data to SSTDR register Data transmission continues? No (3) Read TEND bit in SSSR register (3) When data transmission is completed, the TEND bit is set to 1. Set the TEND bit to 0 and the TE bit to 0 and complete transmit mode.
(2)
Yes
(2) Determine whether data transmission continues.
TEND = 1 ? Yes SSSR register
No
TEND bit 0(1)
SSER register
TE bit 0
End
NOTE: 1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 16.14
Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 322 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.5.3
Data Reception
Figure 16.15 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Reception (Clock Synchronous Communication Mode). During data reception, clock synchronous serial I/O with chip select operates as described below. When the clock synchronous serial I/O with chip select is set as the master device, it outputs a synchronous clock and inputs data. When clock synchronous serial I/O with chip select is set as a slave device, it inputs data synchronized with the input clock. When clock synchronous serial I/O with chip select is set as a master device, it outputs a receive clock and starts receiving by performing dummy read of the SSRDR register. After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI interrupt requests enabled), the RXI interrupt request is generated. If the SSDR register is read, the RDRF bit is automatically set to 0 (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1 byte of data, the receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8 bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to 0 (receive operation is continued after receiving the 1 byte of data) and read the receive data. If the SSRDR register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun error: OEI) and the operation is stopped. When the ORER bit is set to 1, receive cannot be performed. Confirm that the ORER bit is set to 0 before restarting receive. Figure 16.16 shows a Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode).
* SSUMS = 0 (clock synchronous communication mode), CPHS = 0 (data download at even edges), and CPOS bit = 0 ("H" when clock stops)
SSCK
SSI
b0
b7
b0 1 frame
b7
b0
b7
1 frame RDRF bit in SSSR register
1 0 1 0
RXI interrupt request generation RXI interrupt request generation RXI interrupt request generation Dummy read in SSRDR register Read data in SSRDR register Read data in SSRDR register
RSSTP bit in SSCRH register
Processing by program
Set RSSTP bit to 1
Figure 16.15
Example of Clock Synchronous Serial I/O with Chip Select Operation for Data Reception (Clock Synchronous Communication Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 323 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Start
Initialization
(1)
Dummy read of SSRDR register
(2)
Last data received? No
Yes
(1) After setting each register in the clock synchronous serial I/O with chip select register, a dummy read of the SSRDR register is performed and the receive operation is started. (2) Determine whether it is the last 1 byte of data to be received. If so, set to stop after the data is received.
Read ORER bit in SSSR register
Yes (3) ORER = 1 ? No Read RDRF bit in SSSR register (3) If a receive error occurs, perform error (6) Processing after reading the ORER bit. Then set the ORER bit to 0. Transmission/reception cannot be restarted while the ORER bit is set to 1.
(4)
No
RDRF = 1 ? Yes
(4) Confirm that the RDRF bit is set to 1. If the RDRF bit is set to 1, read the receive data in the SSRDR register. When the SSRDR register is read, the RDRF bit is automatically set to 0.
Read receive data in SSRDR register
(5)
SSCRH register
RSSTP bit 1
(5) Before the last 1 byte of data is received, set the RSSTP bit to 1 and stop after the data is received.
Read ORER bit in SSSR register
(6)
ORER = 1 ? No
Yes
Read RDRF in SSSR register
No RDRF = 1 ? (7) Yes SSCRH register RSSTP bit 0
(7) Confirm that the RDRF bit is set to 1. When the receive operation is completed, set the RSSTP bit to 0 and the RE bit to 0 before reading the last 1 byte of data. If the SSRDR register is read before setting the RE bit to 0, the receive operation is restarted again. Overrun error processing
SSER register
RE bit 0
Read receive data in SSRDR register
End
Figure 16.16
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode) Page 324 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.5.4
Data Transmission/Reception
Data transmission/reception is an operation combining data transmission and reception which were described earlier. Transmission/reception is started by writing data to the SSTDR register. When the 8th clock rises or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is transferred from registers SSTDR to SSTRSR), the transmit/receive operation is stopped. When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (Te = RE = 1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1. Figure 16.17 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication Mode).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 325 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Start
Initialization
(1)
Read TDRE bit in SSSR register
TDRE = 1 ? Yes
No
(1) After reading the SSSR register and confirming that the TDRE bit is set to 1, write the transmit data to the SSTDR register. When the transmit data is written to the SSTDR register, the TDRE bit is automatically set to 0.
Write transmit data to SSTDR register
(2)
Read RDRF bit in SSSR register
No RDRF = 1 ? Yes Read receive data in SSRDR register
(2) Confirm that the RDRF bit is set to 1. If the RDRF bit is set to 1, read the receive data in the SSRDR register. When the SSRDR register is read, the RDRF bit is automatically set to 0.
(3)
Data transmission(2) continues? No
Yes
(3) Determine whether the data transmission continues
(4)
Read TEND bit in SSSR register
(4) When the data transmission is completed, the TEND bit in the SSSR register is set to 1.
TEND = 1 ? Yes (5) SSSR register
No
TEND bit 0(1)
(5) Set the TEND bit to 0 and bits RE and TE in (6) the SSER register to 0 before ending transmit/ receive mode.
(6)
SSER register
RE bit 0 TE bit 0
End
NOTE: 1. Write 0 after reading 1 to set the TEND bit to 0.
Figure 16.17
Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 326 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.6
Operation in 4-Wire Bus Communication Mode
In 4-wire bus communication mode, a 4-wire bus consisting of a clock line, a data input line, a data output line, and a chip select line is used for communication. This mode includes bidirectional mode in which the data input line and data output line function as a single pin. The data input line and output line change according to the settings of the MSS bit in the SSCRH register and the BIDE bit in the SSMR2 register. For details, refer to 16.2.2.1 Association between Data I/O Pins and SS Shift Register. In this mode, clock polarity, phase, and data settings are performed by bits CPOS and CPHS in the SSMR register. For details, refer to 16.2.1.1 Association between Transfer Clock Polarity, Phase, and Data. When this MCU is set as the master device, the chip select line controls output. When clock synchronous serial I/O with chip select is set as a slave device, the chip select line controls input. When it is set as the master device, the chip select line controls output of the SCS pin or controls output of a general port according to the setting of the CSS1 bit in the SSMR2 register. When the MCU is set as a slave device, the chip select line sets the SCS pin as an input pin by setting bits CSS1 and CSS0 in the SSMR2 register to 01b. In 4-wire bus communication mode, the MLS bit in the SSMR register is set to 0 and communication is performed MSB-first.
16.2.6.1
Initialization in 4-Wire Bus Communication Mode
Figure 16.18 shows Initialization in 4-Wire Bus Communication Mode. Before the data transit/receive operation, set the TE bit in the SSER register to 0 (transmit disabled), the RE bit in the SSER register to 0 (receive disabled), and initialize the clock synchronous serial I/O with chip select. To change the communication mode or format, set the TE bit to 0 and the RE bit to 0 before making the change. Setting the RE bit to 0 does not change the settings of flags RDRF and ORER or the contents of the SSRDR register.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 327 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Start
SSER register
RE bit 0 TE bit 0 SSUMS bit 1
SSMR2 register
(1)
SSMR register
Set bits CPHS and CPOS MLS bits 0
(1) The MLS bit is set to 0 for MSB-first transfer. The clock polarity and phase are set by bits CPHS and CPOS.
SSCRH register
Set MSS bit (2) Set the BIDE bit to 1 in bidirectional mode and set the I/O of the SCS pin by bits CSS0 and CSS1.
SSMR2 register (2)
SCKS bit 1 Set bits SOOS, CSS0 to CSS1, and BIDE
SSCRH register
Set bits CKS0 to CKS2 Set RSSTP bit ORER bit 0(1)
SSSR register
SSER register
RE bit 1 (receive) TE bit 1 (transmit) Set bits RIE, TEIE, and TIE
End
NOTE: 1. Write 0 after reading 1 to set the ORER bit to 0.
Figure 16.18
Initialization in 4-Wire Bus Communication Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 328 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.6.2
Data Transmission
Figure 16.19 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data Transmission (4-Wire Bus Communication Mode). During the data transmit operation, clock synchronous serial I/O with chip select operates as described below. When the MCU is set as the master device, it outputs a synchronous clock and data. When the MCU is set as a slave device, it outputs data in synchronization with the input clock while the SCS pin is "L". When the transmit data is written to the SSTDR register after setting the TE bit to 1 (transmit enabled), the TDRE bit is automatically set to 0 (data has not been transferred from registers SSTDR to SSTRSR) and the data is transferred from registers SSTDR to SSTRSR. After the TDRE bit is set to 1 (data is transferred from registers SSTDR to SSTRSR), transmission starts. When the TIE bit in the SSER register is set to 1, a TXI interrupt request is generated. After 1 frame of data is transferred while the TDRE bit is set to 0, the data is transferred from registers SSTDR to SSTRSR and transmission of the next frame is started. If the 8th bit is transmitted while TDRE is set to 1, TEND in the SSSR register is set to 1 (when the last bit of the transmit data is transmitted, the TDRE bit is set to 1) and the state is retained. If the TEIE bit in the SSER register is set to 1 (transmit-end interrupt requests enabled), a TEI interrupt request is generated. The SSCK pin remains "H" after transmit-end and the SCS pin is held "H". When transmitting continuously while the SCS pin is held "L", write the next transmit data to the SSTDR register before transmitting the 8th bit. Transmission cannot be performed while the ORER bit in the SSSR register is set to 1 (overrun error). Confirm that the ORER bit is set to 0 before transmission. In contrast to the clock synchronous communication mode, the SSO pin is placed in high-impedance state while the SCS pin is placed in high-impedance state when operating as a master device and the SSI pin is placed in high-impedance state while the SCS pin is placed in "H" input state when operating as a slave device. The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.14 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode)).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 329 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
* CPHS bit = 0 (data change at odd edges) and CPOS bit = 0 ("H" when clock stops)
High-impedance SCS (output)
SSCK
SSO
b7
b6 1 frame
b0
b7
b6 1 frame
b0
TDRE bit in SSSR register
1 0 1 0
Data write to SSTDR register TXI interrupt request is generated TEI interrupt request is generated TXI interrupt request is generated
TEND bit in SSSR register
Processing by program
* CPHS bit = 1 (data change at even edges) and CPOS bit = 0 ("H" when clock stops)
High-impedance SCS (output) SSCK
SSO
b7
b6 1 frame
b0
b7 1 frame
b6
b0
TDRE bit in SSSR register
1 0 1 0
Data write to SSTDR register TXI interrupt request is generated TEI interrupt request is generated TXI interrupt request is generated
TEND bit in SSSR register
Processing by program
CPHS, CPOS: Bits in SSMR register
Figure 16.19
Example of Clock Synchronous Serial I/O with Chip Select Operation during Data Transmission (4-Wire Bus Communication Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 330 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.6.3
Data Reception
Figure 16.20 shows an Example of Clock Synchronous Serial I/O with Chip Select Operation during Data Reception (4-Wire Bus Communication Mode). During data reception, clock synchronous serial I/O with chip select operates as described below. When the MCU is set as the master device, it outputs a synchronous clock and inputs data. When the MCU is set as a slave device, it outputs data synchronized with the input clock while the SCS pin receives "L" input. When the MCU is set as the master device, it outputs a receive clock and starts receiving by performing a dummy read of the SSRDR register. After 8 bits of data are received, the RDRF bit in the SSSR register is set to 1 (data in the SSRDR register) and receive data is stored in the SSRDR register. When the RIE bit in the SSER register is set to 1 (RXI and OEI interrupt requests enabled), an RXI interrupt request is generated. When the SSRDR register is read, the RDRF bit is automatically set to 0 (no data in the SSRDR register). Read the receive data after setting the RSSTP bit in the SSCRH register to 1 (after receiving 1-byte data, the receive operation is completed). Clock synchronous serial I/O with chip select outputs a clock for receiving 8 bits of data and stops. After that, set the RE bit in the SSER register to 0 (receive disabled) and the RSSTP bit to 0 (receive operation is continued after receiving 1-byte data) and read the receive data. When the SSRDR register is read while the RE bit is set to 1 (receive enabled), a receive clock is output again. When the 8th clock rises while the RDRF bit is set to 1, the ORER bit in the SSSR register is set to 1 (overrun error: OEI) and the operation is stopped. When the ORER bit is set to 1, reception cannot be performed. Confirm that the ORER bit is set to 0 before restarting reception. The timing with which bits RDRF and ORER are set to 1 varies depending on the setting of the CPHS bit in the SSMR register. Figure 16.20 shows when bits RDRF and ORER are set to 1. When the CPHS bit is set to 1 (data download at the odd edges), bits RDRF and ORER are set to 1 at some point during the frame. The sample flowchart is the same as that for the clock synchronous communication mode (refer to Figure 16.16 Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication Mode)).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 331 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
* CPHS bit = 0 (data download at even edges) and CPOS bit = 0 ("H" when clock stops)
SCS (output) High-impedance
SSCK
SSI
b7 1 frame
b0
b7 1 frame
b0
b7
b0
RDRF bit in SSSR register
1 0 1 0
Dummy read in SSRDR register Data read in SSRDR register Set RSSTP bit to 1 RXI interrupt request is generated RXI interrupt request is generated
RSSTP bit in SSCRH register
RXI interrupt request is generated
Processing by program
Data read in SSRDR register
* CPHS bit = 1 (data download at odd edges) and CPOS bit = 0 ("H" when clock stops)
High-impedance SCS (output) SSCK
SSI
b7 1 frame
b0
b7 1 frame
b0
b7
b0
RDRF bit in SSSR register
1 0 1 0
Dummy read in SSRDR register Data read in SSRDR register Set RSSTP bit to 1 RXI interrupt request is generated RXI interrupt request is generated
RSSTP bit in SSCRH register
RXI interrupt request is generated
Processing by program
Data read in SSRDR register
CPHS and CPOS: Bit in SSMR register
Figure 16.20
Example of Clock Synchronous Serial I/O with Chip Select Operation during Data Reception (4-Wire Bus Communication Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 332 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.7
SCS Pin Control and Arbitration
When setting the SSUMS bit in the SSMR2 register to 1 (4-wire bus communication mode) and the CSS1 bit in the SSMR2 register to 1 (functions as SCS output pin), set the MSS bit in the SSCRH register to 1 (operates as the master device) and check the arbitration of the SCS pin before starting serial transfer. If clock synchronous serial I/O with chip select detects that the synchronized internal SCS signal is held "L" in this period, the CE bit in the SSSR register is set to 1 (conflict error) and the MSS bit is automatically set to 0 (operates as a slave device). Figure 16.21 shows the Arbitration Check Timing. Future transmit operations are not performed while the CE bit is set to 1. Set the CE bit to 0 (no conflict error) before starting transmission.
SCS input
Internal SCS (synchronization) MSS bit in SSCRH register 1 0
Transfer start
CE
Data write to SSTDR register
High-impedance SCS output Maximum time of SCS internal synchronization
During arbitration detection
Figure 16.21
Arbitration Check Timing
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 333 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.2.8
Notes on Clock Synchronous Serial I/O with Chip Select
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use the clock synchronous serial I/O with chip select function.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 334 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3
I2C bus Interface
The I2C bus interface is the circuit that performs serial communication based on the data transfer format of the Philips I2C bus. Table 16.5 lists the I2C bus Interface Specifications, Figure 16.22 shows a Block Diagram of I2C bus interface, and Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.24 to 16.31 show the registers associated with the I2C bus interface. * I2C bus is a trademark of Koninklijke Philips Electronics N. V. Table 16.5 I2C bus Interface Specifications
Item Specification 2C bus format Communication formats * I - Selectable as master/slave device - Continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent) - Start/stop conditions are automatically generated in master mode - Automatic loading of acknowledge bit during transmission - Bit synchronization/wait function (In master mode, the state of the SCL signal is monitored per bit and the timing is synchronized automatically. If the transfer is not possible yet, the SCL signal goes "L" and the interface stands by.) - Support for direct drive of pins SCL and SDA (N-channel open drain output) * Clock synchronous serial format - Continuous transmit/receive operation (because the shift register, transmit data register, and receive data register are independent) I/O pins SCL (I/O): Serial clock I/O pin SDA (I/O): Serial data I/O pin Transfer clocks * When the MST bit in the ICCR1 register is set to 0 The external clock (input from the SCL pin) * When the MST bit in the ICCR1 register is set to 1 The internal clock selected by bits CKS0 to CKS3 in the ICCR1 register (output from the SCL pin) Receive error detection * Overrun error detection (clock synchronous serial format) Indicates an overrun error during reception. When the last bit of the next data item is received while the RDRF bit in the ICSR register is set to 1 (data in the ICDRR register), the AL bit is set to 1. 2C bus format .................................. 6 sources(1) Interrupt sources *I Transmit data empty (including when slave address matches), transmit ends, receive data full (including when slave address matches), arbitration lost, NACK detection, and stop condition detection. * Clock synchronous serial format ...... 4 sources(1) Transmit data empty, transmit ends, receive data full and overrun error 2C bus format Select functions *I - Selectable output level for acknowledge signal during reception * Clock synchronous serial format - MSB-first or LSB-first selectable as data transfer direction NOTE: 1. All sources use one interrupt vector for I2C bus interface.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 335 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
f1
Transfer clock generation circuit Output control Transmit/receive control circuit Noise canceller ICDRT register Output control SAR register ICDRS register
Data bus
SCL
ICCR1 register ICCR2 register ICMR register
SDA
Noise canceller
Address comparison circuit
ICDRR register Bus state judgment circuit Arbitration judgment circuit ICIER register
ICSR register
Interrupt generation circuit Interrupt request (TXI, TEI, RXI, STPI, NAKI)
Figure 16.22
Block Diagram of I2C bus interface
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 336 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
VCC
VCC
SCL SCL input SCL output
SCL
SDA SDA input SDA output SCL (Master) SCL input SCL output SCL input SCL output SCL
SDA
SDA SDA input SDA output (Slave 1) SDA input SDA output (Slave 2)
SDA
Figure 16.23
External Circuit Connection Example of Pins SCL and SDA
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 337 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
IIC bus Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ICCR1 Bit Symbol
CKS0
CKS1
CKS2
CKS3
Address 00B8h Bit Name Transmit clock select bits 3 to b3 b2 b1 b0 0 0 0 0 : f1/28 0(1) 0 0 0 1 : f1/40 0 0 1 0 : f1/48 0 0 1 1 : f1/64 0 1 0 0 : f1/80 0 1 0 1 : f1/100 0 1 1 0 : f1/112 0 1 1 1 : f1/128 1 0 0 0 : f1/56 1 0 0 1 : f1/80 1 0 1 0 : f1/96 1 0 1 1 : f1/128 1 1 0 0 : f1/160 1 1 0 1 : f1/200 1 1 1 0 : f1/224 1 1 1 1 : f1/256 Transfer/receive select bit
b5 b4
After Reset 00h Function
RW
RW
RW
RW
RW
TRS
(2, 3, 6)
Master/slave select bit(5, 6) MST Receive disable bit RCVD
0 0 : Slave Receive Mode(4) 0 1 : Slave Transmit Mode 1 0 : Master Receive Mode 1 1 : Master Transmit Mode After reading the ICDRR register w hile the TRS bit is set to 0 0 : Maintains the next receive operation 1 : Disables the next receive operation 0 : This module is halted (Pins SCL and SDA are set to port function) 1 : This module is enabled for transfer operations (Pins SCL and SDA are bus drive state)
RW
RW
RW
IIC bus interface enable bit ICE
RW
NOTES: 1. Set according to the necessary transfer rate in master mode. Refer to Table 16.6 Transfer Rate Examples for the transfer rate. This bit is used for maintaining of the setup time in transmit mode of slave mode. The time is 10Tcyc w hen the CKS3 bit is set to 0 and 20Tcyc w hen the CKS3 bit is set to 1. (1Tcyc = 1/f1(s)) 2. Rew rite the TRS bit betw een transfer frames. 3. When the first 7 bit after the start condition in slave receive mode match w ith the slave address set in the SAR register and the 8th bit is set to 1, the TRS bit is set to 1. 4. In master mode w ith the I2C bus format, w hen arbitration is lost, bits MST and TRS are set to 0 and the IIC enters slave receive mode. 5. When an overrun error occurs in master receive mode of the clock synchronous serial format, the MST bit is set to 0 and the IIC enters slave receive mode. 6. In multimaster operation use the MOV instruction to set bits TRS and MST.
Figure 16.24
ICCR1 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 338 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
IIC bus Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address 00B9h ICCR2 Bit Symbol Bit Name -- Nothing is assigned. If necessary, set to 0. (b0) When read, the content is 1. IIC control part reset bit IICRST
After Reset 01111101b Function
RW --
When hang-up occurs due to communication failure during I2C bus interface operation, w rite 1, to reset the control block of the I2C bus interface w ithout setting ports or initializing registers.
RW
-- (b2) SCLO SDAOP
Nothing is assigned. If necessary, set to 0. When read, the content is 1. SCL monitor flag SDAO w rite protect bit 0 : SCL pin is set to "L" 1 : SCL pin is set to "H" When rew rite to SDAO bit, w rite 0 simultaneously. When read, the content is 1.
(1)
-- RO RW
SDAO
SDA output value control When read bit 0 : SDA pin output is held "L" 1 : SDA pin output is held "H" When w ritten(1,2) 0 : SDA pin output is changed to "L" 1 : SDA pin output is changed to high-impedance ("H" output via external pull-up resistor) Start/stop condition generation disable bit When w riting to the to BBSY bit, w rite 0 simultaneously.(3) When read, the content is 1. Writing 1 is invalid. When read 0 : Bus is in released state (SDA signal changes from "L" to "H" w hile SCL signal is in "H" state) 1 : Bus is in occupied state (SDA signal changes from "H" to "L" w hile SCL signal is in "H" state) When w ritten(3) 0 : Generates stop condition 1 : Generates start condition
RW
SCP
RW
Bus busy bit(4)
BBSY
RW
NOTES: 1. When w riting to the SDAO bit, w rite 0 to the SDAOP bit using the MOV instruction simultaneously. 2. Do not w rite during a transfer operation. 3. This bit is enabled in master mode. When w riting to the BBSY bit, w rite 0 to the SCP bit using the MOV instruction simultaneously. Execute the same w ay w hen the start condition is regenerating. 4. This bit is disabled w hen the clock synchronous serial format is used.
Figure 16.25
ICCR2 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 339 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
IIC bus Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ICMR Bit Symbol
Address 00BAh Bit Name Bits counter 2 to 0
After Reset 00011000b Function I2C bus format (remaining transfer bit count w hen read out and data bit count of next transfer w hen w ritten).(1,2)
b2 b1 b0
RW
BC0
BC1
0 0 0 : 9 bits (3) 0 0 1 : 2 bits 0 1 0 : 3 bits 0 1 1 : 4 bits 1 0 0 : 5 bits 1 0 1 : 6 bits 1 1 0 : 7 bits 1 1 1 : 8 bits Clock synchronous serial format (w hen read, the remaining transfer bit count and w hen w ritten 000b).
b2 b1 b0
RW
RW
BC2
0 0 0 : 8 bits 0 0 1 : 1 bit 0 1 0 : 2 bits 0 1 1 : 3 bits 1 0 0 : 4 bits 1 0 1 : 5 bits 1 1 0 : 6 bits 1 1 1 : 7 bits BC w rite protect bit When rew riting bits BC0 to BC2, w rite 0 simultaneously.(2,4) When read, the content is 1.
RW
BCWP -- (b4) -- (b5)
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 1. Reserved bit Wait insertion bit(5) Set to 0. 0 : No w ait (Transfer data and acknow ledge bit consecutively) 1 : Wait (After the clock falls for the final data bit, "L" period is extended for tw o transfer clocks cycles) 0 : Data transfer w ith MSB-first(6) 1 : Data transfer w ith LSB-first
-- RW
WAIT
RW
MLS
MSB-first/LSB-first select bit
RW
NOTES: 1. Rew rite betw een transfer frames. When w riting values other than 000b, w rite w hen the SCL signal is "L". 2. When w riting to bits BC0 to BC2, w rite 0 to the BCWP bit using the MOV instruction. 3. After data including the acknow ledge bit is transferred, these bits are automatically set to 000b. When the start condition is detected, these bits are automatically set to 000b. 4. Do not rew rite w hen the clock synchronous serial format is used. 5. The setting value is enabled in master mode of the I2C bus format. It is disabled in slave mode of the I2C bus format or w hen the clock synchronous serial format is used. 6. Set to 0 w hen the I2C bus format is used.
Figure 16.26
ICMR Register Page 340 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
IIC bus Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ICIER Bit Symbol
ACKBT
Address 00BBh Bit Name Transmit acknow ledge select bit
After Reset 00h Function 0 : 0 is transmitted as acknow ledge bit in receive mode. 1 : 1 is transmitted as acknow ledge bit in receive mode. 0 : Acknow ledge bit received from receive device in transmit mode is set to 0. 1 : Acknow ledge bit received from receive device in transmit mode is set to 1.
RW
RW
Receive acknow ledge bit ACKBR
RO
ACKE
Acknow ledge bit judgment 0 : Value of receive acknow ledge bit is ignored select bit and continuous transfer is performed. 1 : When receive acknow ledge bit is set to 1, continuous transfer is halted. Stop condition detection interrupt enable bit 0 : Disables stop condition detection interrupt request 1 : Enables stop condition detection interrupt request(2) 0 : Disables NACK receive interrupt request and arbitration lost/overrun error interrupt request 1 : Enables NACK receive interrupt request and arbitration lost/overrun error interrupt request(1) 0 : Disables receive data full and overrun error interrupt request 1 : Enables receive data full and overrun error interrupt request(1) 0 : Disables transmit end interrupt request 1 : Enables transmit end interrupt request 0 : Disables transmit data empty interrupt request 1 : Enables transmit data empty interrupt request
RW
STIE
RW
NAKIE
NACK receive interrupt enable bit
RW
RIE
Receive interrupt enable bit
RW
TEIE
Transmit end interrupt enable bit Transmit interrupt enable bit
RW
TIE
RW
NOTES: 1. An overrun error interrupt request is generated w hen the clock synchronous format is used. 2. Set the STIE bit to 1 (enable stop condition detection interrupt request) w hen the STOP bit in the ICSR register is set to 0.
Figure 16.27
ICIER Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 341 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
IIC bus Status Register(7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ICSR Bit Symbol ADZ
Address 00BCh Bit Name General call address recognition flag(1,2)
After Reset 0000X000b Function When the general call address is detected, this flag is set to 1.
RW RW
AAS
Slave address recognition This flag is set to 1 w hen the first frame follow ing start condition matches bits SVA0 to SVA6 in the flag(1) SAR register in slave receive mode. (Detect the slave address and generate call address) Arbitration lost flag/overrun error flag(1) When the I2C bus format is used, this flag indicates that arbitration has been lost in master mode. In the follow ing cases, this flag is set to 1(3). * When the internal SDA signal and SDA pin level do not match at the rise of the SCL signal in master transmit mode * When the start condition is detected and the SDA pin is held "H" in master transmit/receive mode This flag indicates an overrun error w hen the clock synchronous format is used. In the follow ing case, this flag is set to 1. * When the last bit of the next data item is received w hile the RDRF bit is set to 1 When the stop condition is detected after the frame is transferred, this flag is set to 1.
RW
AL
RW
STOP NACKF RDRF
Stop condition detection flag(1)
RW RW RW
No acknow ledge detection When no acknow ledge is detected from the receive flag(1,4) device after transmission, this flag is set to 1. Receive data register full(1,5) Transmit end(1,6) When receive data is transferred from in registers ICDRS to ICDRR , this flag is set to 1. When the 9th clock cycle of the SCL signal in the I2C bus format occurs w hile the TDRE bit is set to 1, this flag is set to 1. This flag is set to 1 w hen the final bit of the transmit frame is transmitted in the clock synchronous format. In the follow ing cases, this flag is set to 1. * Data is transferred from registers ICDRT to ICDRS and the ICDRT register is empty * When setting the TRS bit in the ICCR1 register to 1 (transmit mode) * When generating the start condition (including retransmit) * When changing from slave receive mode to slave transmit mode
TEND
RW
Transmit data empty (1,6)
TDRE
RW
NOTES: 1. Each bit is set to 0 by reading 1 before w riting 0. 2. This flag is enabled in slave receive mode of the I2C bus format. 3. When tw o or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus Interface monitors the SDA pin and the data w hich the I2C bus Interface transmits is different, the AL flag is set to 1 and the bus is occupied by another master. 4. The NACKF bit is enabled w hen the ACKE bit in the ICIER register is set to 1 (w hen the receive acknow ledge bit is set to 1, transfer is halted). 5. The RDRF bit is set to 0 w hen reading data from the ICDRR register. 6. Bits TEND and TDRE are set to 0 w hen w riting data to the ICDRT register. 7. When accessing the ICSR register continuously, insert one or more NOP instructions betw een the instructions to access it.
Figure 16.28
ICSR Register Page 342 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Slave Address Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SAR Bit Symbol FS SVA0 SVA1 SVA2 SVA3 SVA4 SVA5 SVA6
Address 00BDh Bit Name Format select bit Slave address 6 to 0
After Reset 00h Function 0 : I2C bus format 1 : Clock synchronous serial format Set an address different from that of the other slave devices w hich are connected to the I2C bus. When the 7 high-order bits of the first frame transmitted after the starting condition match bits SVA0 to SVA6 in slave mode of the I2C bus format, the MCU operates as a slave device.
RW RW RW RW RW RW RW RW RW
IIC bus Transmit Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ICDRT
Address 00BEh
After Reset FFh RW
Function Store transmit data When it is detected that the ICDRS register is empty, the stored transmit data item is transferred to the ICDRS register and data transmission starts. When the next transmit data item is w ritten to the ICDRT register during transmission of the data in the ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR register is set to 1 (data transferred LSB-first) and after the data is w ritten to the ICDRT register, the MSB-LSB inverted data is read.
RW
Figure 16.29
Registers SAR and ICDRT
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 343 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
IIC bus Receive Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ICDRR
Address 00BFh
After Reset FFh RW RO
Function Store receive data When the ICDRS register receives 1 byte of data, the receive data is transferred to the ICDRR register and the next receive operation is enabled.
IIC bus Shift Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ICDRS Function This register is used to transmit and receive data. The transmit data is transferred from registers ICRDT to the ICDRS and data is transmitted from the SDA pin w hen transmitting. After 1 byte of data received, data is transferred from registers ICDRS to ICDRR w hile receiving. RW
--
Figure 16.30
Registers ICDRR and ICDRS
Port Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
00
0000
Symbol Address 00F8h PMR Bit Symbol Bit Name Reserved bits -- (b3-b0) U1PINSEL -- (b6-b5) IICSEL Port CLK1/TXD1/RXD1 sw itch bit Reserved bits SSU / I2C bus sw itch bit
After Reset 00h Function Set to 0. 0 : I/O ports P6_5, P6_6, P6_7 1 : CLK1, TXD1, RXD1 Set to 0. 0 : Selects SSU function 1 : Selects I2C bus function
RW -- RW -- RW
Figure 16.31
PMR Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 344 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.1
Transfer Clock
When the MST bit in the ICCR1 register is set to 0, the transfer clock is the external clock input from the SCL pin. When the MST bit in the ICCR1 register is set to 1, the transfer clock is the internal clock selected by bits CKS0 to CKS3 in the ICCR1 register and the transfer clock is output from the SCL pin. Table 16.6 lists the Transfer Rate Examples. Table 16.6 Transfer Rate Examples
ICCR1 Register Transfer Transfer Rate Clock f1 = 5 MHz f1 = 8 MHz f1 = 10 MHz f1 = 16 MHz f1 = 20 MHz CKS3 CKS2 CKS1 CKS0 0 0 0 0 f1/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 f1/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 1 0 f1/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 f1/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 1 0 0 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 f1/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz 1 0 f1/112 44.6 kHz 71.4 kHz 89.3 kHz 143 kHz 179 kHz 1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 1 0 0 0 f1/56 89.3 kHz 143 kHz 179 kHz 286 kHz 357 kHz 1 f1/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 0 f1/96 52.1 kHz 83.3 kHz 104 kHz 167 kHz 208 kHz 1 f1/128 39.1 kHz 62.5 kHz 78.1 kHz 125 kHz 156 kHz 1 0 0 f1/160 31.3 kHz 50.0 kHz 62.5 kHz 100 kHz 125 kHz 1 f1/200 25.0 kHz 40.0 kHz 50.0 kHz 80.0 kHz 100 kHz 1 0 f1/224 22.3 kHz 35.7 kHz 44.6 kHz 71.4 kHz 89.3 kHz 1 f1/256 19.5 kHz 31.3 kHz 39.1 kHz 62.5 kHz 78.1 kHz
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 345 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.2
Interrupt Requests
I2 C
The bus interface has six interrupt requests when the I2C bus format is used and four interrupt requests when the clock synchronous serial format is used. Table 16.7 lists the Interrupt Requests of I2C bus Interface. Since these interrupt requests are allocated at the I2C bus interface interrupt vector table, determining the source bit by bit is necessary. Table 16.7 Interrupt Requests of I2C bus Interface Interrupt Request Generation Condition I2C bus Format Clock Synchronous Serial Enabled Enabled Enabled Disabled Disabled Enabled
Transmit data empty Transmit ends Receive data full Stop condition detection NACK detection Arbitration lost/overrun error
TXI TEI RXI STPI NAKI
TIE = 1 and TDRE = 1 TEIE = 1 and TEND = 1 RIE = 1 and RDRF = 1 STIE = 1 and STOP = 1 NAKIE = 1 and AL = 1 (or NAKIE = 1 and NACKF = 1)
Enabled Enabled Enabled Enabled Enabled Enabled
STIE, NAKIE, RIE, TEIE, TIE: Bits in ICIER register AL, STOP, NACKF, RDRF, TEND, TDRE: Bits in ICSR register When the generation conditions listed in Table 16.7 are met, an I2C bus interface interrupt request is generated. Set the interrupt generation conditions to 0 by the I2C bus interface interrupt routine. However, bits TDRE and TEND are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is automatically set to 0 by reading the ICDRR register. When writing transmit data to the ICDRT register, the TDRE bit is set to 0. When data is transferred from registers ICDRT to ICDRS, the TDRE bit is set to 1 and by further setting the TDRE bit to 0, 1 additional byte may be transmitted. Set the STIE bit to 1 (enable stop condition detection interrupt request) when the STOP bit is set to 0.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 346 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.3
I2C bus Interface Mode I2C bus Format
16.3.3.1
Setting the FS bit in the SAR register to 0 enables communication in I2C bus format. Figure 16.32 shows the I2C bus Format and Bus Timing. The 1st frame following the start condition consists of 8 bits.
(1) I2C bus format (a) I2C bus format (FS = 0)
S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 Transfer bit count (n = 1 to 8) Transfer frame count (m = from 1)
(b) I2C bus format (when start condition is retransmitted, FS = 0)
S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1
Upper: Transfer bit count (n1, n2 = 1 to 8) Lower: Transfer frame count (m1, m2 = 1 or more)
(2) I2C bus timing
SDA
SCL
1 to 7
8
9
1 to 7
8
9
1 to 7
8
9
S
SLA
R/W
A
DATA
A
DATA
A
P
Explanation of symbols S : Start condition The master device changes the SDA signal from "H" to "L" while the SCL signal is held "H". SLA : Slave address R/W : Indicates the direction of data transmit/receive Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when R/W value is 0. A : Acknowledge The receive device sets the SDA signal to "L". DATA : Transmit / receive data P : Stop condition The master device changes the SDA signal from "L" to "H" while the SCL signal is held "H".
Figure 16.32
I2C bus Format and Bus Timing
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 347 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.3.2
Master Transmit Operation
In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figures 16.33 and 16.34 show the Operating Timing in Master Transmit Mode (I2C bus Interface Mode). The transmit procedure and operation in master transmit mode are as follows. (1) Set the STOP bit in the ICSR register to 0 to reset it. Then set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Then set bits WAIT and MLS in the ICMR register and set bits CKS0 to CKS3 in the ICCR1 register (initial setting). (2) Read the BBSY bit in the ICCR2 register to confirm that the bus is free. Set bits TRS and MST in the ICCR1 register to master transmit mode. The start condition is generated by writing 1 to the BBSY bit and 0 to the SCP bit by the MOV instruction. (3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from registers ICDRT to ICDRS), write transmit data to the ICDRT register (data in which a slave address and R/W are indicated in the 1st byte). At this time, the TDRE bit is automatically set to 0, data is transferred from registers ICDRT to ICDRS, and the TDRE bit is set to 1 again. (4) When transmission of 1 byte of data is completed while the TDRE bit is set to 1, the TEND bit in the ICSR register is set to 1 at the rise of the 9th transmit clock pulse. Read the ACKBR bit in the ICIER register, and confirm that the slave is selected. Write the 2nd byte of data to the ICDRT register. Since the slave device is not acknowledged when the ACKBR bit is set to 1, generate the stop condition. The stop condition is generated by the writing 0 to the BBSY bit and 0 to the SCP bit by the MOV instruction. The SCL signal is held "L" until data is available and the stop condition is generated. (5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1. (6) When writing the number of bytes to be transmitted to the ICDRT register, wait until the TEND bit is set to 1 while the TDRE bit is set to 1. Or wait for NACK (the NACKF bit in the ICSR register is set to 1) from the receive device while the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit is set to 1, transfer is halted). Then generate the stop condition before setting bits TEND and NACKF to 0. (7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 348 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SCL (master output)
1
2
3
4
5
6
7
8
9
1
2
SDA (master output)
b7
b6
b5
b4
b3
b2
b1
b0
b7
b6
Slave address SDA (slave output)
R/W A
TDRE bit in ICSR register
1 0 1 0
TEND bit in ICSR register
ICDRT register
Address + R/W
Data 1
Data 2
ICDRS register
Address + R/W
Data 1
Processing by program
(2) Instruction of start condition generation
(3) Data write to ICDRT register (1st byte)
(4) Data write to ICDRT register (2nd byte)
(5) Data write to ICDRT register (3rd byte)
Figure 16.33
Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (1)
SCL (master output)
9
1
2
3
4
5
6
7
8
9
SDA (master output)
b7
b6
b5
b4
b3
b2
b1
b0
SDA (slave output)
A
A/A
TDRE bit in ICSR register
1 0 1 0
TEND bit in ICSR register
ICDRT register
Data n
ICDRS register
Data n
Processing by program
(3) Data write to ICDRT register
(6) Generate stop condition and set TEND bit to 0 (7) Set to slave receive mode
Figure 16.34
Operating Timing in Master Transmit Mode (I2C bus Interface Mode) (2)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 349 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.3.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. Figures 16.35 and 16.36 show the Operating Timing in Master Receive Mode (I2C bus Interface Mode). The receive procedure and operation in master receive mode are shown below. (1) After setting the TEND bit in the ICSR register to 0, switch from master transmit mode to master receive mode by setting the TRS bit in the ICCR1 register to 0. Also, set the TDRE bit in the ICSR register to 0. (2) When performing the dummy read of the ICDRR register and starting the receive operation, the receive clock is output in synchronization with the internal clock and data is received. The master device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rising edge of the 9th clock cycle of the receive clock. (3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the 9th clock cycle. At this time, when reading the ICDRR register, the received data can be read and the RDRF bit is set to 0 simultaneously. (4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls after the ICDRR register is read by another process while the RDRF bit is set to 1, the SCL signal is fixed "L" until the ICDRR register is read. (5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (disables the next receive operation) before reading the ICDRR register, stop condition generation is enabled after the next receive operation. (6) When the RDRF bit is set to 1 at the rise of the 9th clock cycle of the receive clock, generate the stop condition. (7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0 (maintain the following receive operation). (8) Return to slave receive mode.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 350 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Master transmit mode SCL (master output)
Master receive mode
9
1
2
3
4
5
6
7
8
9
1
SDA (master output)
A
SDA (slave output)
A
b7
b6
b5
b4
b3
b2
b1
b0
b7
TDRE bit in ICSR register
1 0
TEND bit in ICSR register
1 0 1 0 1 0
TRS bit in ICCR1 register
RDRF bit in ICSR register
ICDRS register
Data 1
ICDRR register
Data 1
Processing by program
(1) Set TEND and TRS bits to 0 before setting TDRE bits to 0
(2) Read ICDRR register
(3) Read ICDRR register
Figure 16.35
Operating Timing in Master Receive Mode (I2C bus Interface Mode) (1)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 351 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SCL (master output)
9
1
2
3
4
5
6
7
8
9
SDA (master output)
A
A/A
SDA (slave output)
b7
b6
b5
b4
b3
b2
b1
b0
RDRF bit in ICSR register
1 0 1 0
RCVD bit in ICCR1 register
ICDRS register
Data n-1
Data n
ICDRR register
Data n-1
Data n
Processing by program
(5) Set RCVD bit to 1 before reading ICDRR register
(6) Stop condition generation
(7) Read ICDRR register before setting RCVD bit to 0 (8) Set to slave receive mode
Figure 16.36
Operating Timing in Master Receive Mode (I2C bus Interface Mode) (2)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 352 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.3.4
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data while the master device outputs the receive clock and returns an acknowledge signal. Figures 16.37 and 16.38 show the Operating Timing in Slave Transmit Mode (I2C bus Interface Mode). The transmit procedure and operation in slave transmit mode are as follows. (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode. (2) When the slave address matches at the 1st frame after detecting the start condition, the slave device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock cycle. At this time, if the 8th bit of data (R/W) is 1, bits TRS and TDRE in the ICSR register are set to 1, and the mode is switched to slave transmit mode automatically. Continuous transmission is enabled by writing transmit data to the ICDRT register every time the TDRE bit is set to 1. (3) When the TDRE bit in the ICDRT register is set to 1 after writing the last transmit data to the ICDRT register, wait until the TEND bit in the ICSR register is set to 1 while the TDRE bit is set to 1. When the TEND bit is set to 1, set the TEND bit to 0. (4) The SCL signal is released by setting the TRS bit to 0 and performing a dummy read of the ICDRR register to end the process. (5) Set the TDRE bit to 0.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 353 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Slave receive mode SCL (master output)
Slave transmit mode
9
1
2
3
4
5
6
7
8
9
1
SDA (master output)
A
SCL (slave output)
SDA (slave output)
A
b7
b6
b5
b4
b3
b2
b1
b0
b7
TDRE bit in ICSR register
1 0 1 0 1 0
TEND bit in ICSR register
TRS bit in ICCR1 register
ICDRT register
Data 1
Data 2
Data 3
ICDRS register
Data 1
Data 2
ICDRR register
Processing by program
(1) Data write to ICDRT register (data 1)
(2) Data write to ICDRT register (data 2)
(2) Data write to ICDRT register (data 3)
Figure 16.37
Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (1)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 354 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Slave receive mode Slave transmit mode SCL (master output)
9
1
2
3
4
5
6
7
8
9
SDA (master output)
A
A
SCL (slave output)
SDA (slave output)
b7
b6
b5
b4
b3
b2
b1
b0
TDRE bit in ICSR register
1 0
TEND bit in ICSR register
1 0 1 0
TRS bit in ICCR1 register
ICDRT register
Data n
ICDRS register
Data n
ICDRR register
Processing by program
(3) Set the TEND bit to 0
(4) Dummy read of ICDRR register after setting TRS bit to 0
(5) Set TDRE bit to 0
Figure 16.38
Operating Timing in Slave Transmit Mode (I2C bus Interface Mode) (2)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 355 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.3.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an acknowledge signal. Figures 16.39 and 16.40 show the Operating Timing in Slave Receive Mode (I2C bus Interface Mode). The receive procedure and operation in slave receive mode are as follows. (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits WAIT and MLS in the ICMR register and bits CKS0 to CKS3 in the ICCR1 register (initial setting). Set bits TRS and MST in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode. (2) When the slave address matches at the 1st frame after detecting the start condition, the slave device outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock cycle. Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy read (the read data is unnecessary because it indicates the slave address and R/W). (3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock cycle falls while the RDRF bit is set to 1, the SCL signal is fixed "L" until the ICDRR register is read. The setting change of the acknowledge signal returned to the master device before reading the ICDRR register takes affect from the following transfer frame. (4) Reading the last byte is performed by reading the ICDRR register in like manner.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 356 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
SCL (master output)
9
1
2
3
4
5
6
7
8
9
1
SDA (master output)
b7
b6
b5
b4
b3
b2
b1
b0
b7
SCL (slave output)
SDA (slave output)
A
A
RDRF bit in ICSR register
1 0
ICDRS register
Data 1
Data 2
ICDRR register
Data 1
Processing by program
(2) Dummy read of ICDRR register
(2) Read ICDRR register
Figure 16.39
Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (1)
SCL (master output)
9
1
2
3
4
5
6
7
8
9
SDA (master output)
b7
b6
b5
b4
b3
b2
b1
b0
SCL (slave output)
SDA (slave output)
A
A
RDRF bit in ICSR register
1 0
ICDRS register
Data 1
Data 2
ICDRR register
Data 1
Processing by program
(3) Set ACKBT bit to 1
(3) Read ICDRR register
(4) Read ICDRR register
Figure 16.40
Operating Timing in Slave Receive Mode (I2C bus Interface Mode) (2)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 357 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.4
Clock Synchronous Serial Mode Clock Synchronous Serial Format
16.3.4.1
Set the FS bit in the SAR register to 1 to use the clock synchronous serial format for communication. Figure 16.41 shows the Transfer Format of Clock Synchronous Serial Format. When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin, and when the MST bit is set to 0, the external clock is input. The transfer data is output between successive falling edges of the SCL clock, and data is determined at the rising edge of the SCL clock. MSB-first or LSB-first can be selected as the order of the data transfer by setting the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register during transfer standby.
SCL
SDA
b0
b1
b2
b3
b4
b5
b6
b7
Figure 16.41
Transfer Format of Clock Synchronous Serial Format
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 358 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.4.2
Transmit Operation
In transmit mode, transmit data is output from the SDA pin in synchronization with the falling edge of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0. Figure 16.42 shows the Operating Timing in Transmit Mode (Clock Synchronous Serial Mode). The transmit procedure and operation in transmit mode are as follows. (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the ICCR1 register and set the MST bit (initial setting). (2) The TDRE bit in the ICSR register is set to 1 by selecting transmit mode after setting the TRS bit in the ICCR1 register to 1. (3) Data is transferred from registers ICDRT to ICDRS and the TDRE bit is automatically set to 1 by writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1. Continuous transmission is enabled by writing data to the ICDRT register every time the TDRE bit is set to 1. When switching from transmit to receive mode, set the TRS bit to 0 while the TDRE bit is set to 1.
SCL
1
2
7
8
1
7
8
1
SDA (output)
b0
b1
b6
b7
b0
b6
b7
b0
TRS bit in ICCR1 register
1 0 1 0
TDRE bit in ICSR register
ICDRT register
Data 1
Data 2
Data 3
ICDRS register
Data 1
Data 2
Data 3
Processing by program
(3) Data write to ICDRT register (2) Set TRS bit to 1
(3) Data write to ICDRT register
(3) Data write to ICDRT register
(3) Data write to ICDRT register
Figure 16.42
Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 359 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.4.3
Receive Operation
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0. Figure 16.43 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode). The receive procedure and operation in receive mode are as follows. (1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the ICCR1 register and set the MST bit (initial setting). (2) The output of the receive clock starts when the MST bit is set to 1 while the transfer clock is being output. (3) Data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1, when the receive operation is completed. Since the next byte of data is enabled when the MST bit is set to 1, the clock is output continuously. Continuous reception is enabled by reading the ICDRR register every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock cycle while the RDRF bit is set to 1, and the AL bit in the ICSR register is set to 1. At this time, the last receive data is retained in the ICDRR register. (4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the next receive operation) and read the ICDRR register. The SCL signal is fixed "H" after reception of the following byte of data is completed.
SCL
1
2
7
8
1
7
8
1
2
SDA (input)
b0
b1
b6
b7
b0
b6
b7
b0
MST bit in ICCR1 register
1 0 1 0
TRS bit in ICCR1 register
RDRF bit in ICSR register
1 0
ICDRS register
Data 1
Data 2
Data 3
ICDRR register
Data 1
Data 2
Processing by program
(2) Set MST bit to 1 (when transfer clock is output)
(3) Read ICDRR register
(3) Read ICDRR register
Figure 16.43
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 360 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.5
Noise Canceller
The states of pins SCL and SDA are routed through the noise canceller before being latched internally. Figure 16.44 shows a Block Diagram of Noise Canceller. The noise canceller consists of two cascaded latch and match detector circuits. When the SCL pin input signal (or SDA pin input signal) is sampled on f1 and two latch outputs match, the level is passed forward to the next circuit. When they do not match, the former value is retained.
f1 (sampling clock)
C SCL or SDA input signal D Latch Q D
C Q Latch
Match detection circuit
Internal SCL or SDA signal
Period of f1
f1 (sampling clock)
Figure 16.44
Block Diagram of Noise Canceller
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 361 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.6
Bit Synchronization Circuit
When setting the I2C bus interface to master mode, the high-level period may become shorter in the following two cases: * If the SCL signal is driven L level by a slave device * If the rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line. Therefore, the SCL signal is monitored and communication is synchronized bit by bit. Figure 16.45 shows the Timing of Bit Synchronization Circuit, and Table 16.8 lists the Time between Changing SCL Signal from "L" Output to High-Impedance and Monitoring of SCL Signal.
Reference clock of SCL monitor timing
SCL
VIH
Internal SCL
Figure 16.45
Timing of Bit Synchronization Circuit
Table 16.8
Time between Changing SCL Signal from "L" Output to High-Impedance and Monitoring of SCL Signal ICCR1 Register CKS3 0 1 CKS2 0 1 0 1 Time for Monitoring SCL 7.5Tcyc 19.5Tcyc 17.5Tcyc 41.5Tcyc
1Tcyc = 1/f1(s)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 362 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.7
Examples of Register Setting
Figures 16.46 to 16.49 show Examples of Register Setting When Using I2C bus interface.
Start Initial setting Read BBSY bit in ICCR2 register (1) Judge the state of the SCL and SDA lines No (1) BBSY = 0 ? (3) Generate the start condition Yes ICCR1 register TRS bit 1 MST bit 1 SCP bit 0 BBSY bit 1 (2) (4) Set the transmit data of the 1st byte (slave address + R/W) (5) Wait for 1 byte to be transmitted ICCR2 register (3) (6) Judge the ACKBR bit from the specified slave device (7) Set the transmit data after 2nd byte (except the last byte) (8) Wait until the ICRDT register is empty Read TEND bit in ICSR register (9) Set the transmit data of the last byte No (5) TEND = 1 ? (10) Wait for end of transmission of the last byte (11) Set the TEND bit to 0 Yes Read ACKBR bit in ICIER register (12) Set the STOP bit to 0 (13) Generate the stop condition ACKBR = 0 ? Yes Transmit mode ? Yes Write transmit data to ICDRT register Read TDRE bit in ICSR register (8) TDRE = 1 ? Yes No Last byte ? (9) Yes Write transmit data to ICDRT register Read TEND bit in ICSR register (10) TEND = 1 ? Yes ICSR register ICSR register ICCR2 register TEND bit 0 STOP bit 0 SCP bit 0 BBSY bit 0 (11) (12) (13) (7) No No (6) (14) Wait until the stop condition is generated (15) Set to slave receive mode Set the TDRE bit to 0 Master receive mode (2) Set to master transmit mode * Set the STOP bit in the ICSR register to 0 * Set the IICSEL bit in the PMR register to 1
Write transmit data to ICDRT register
(4)
No
No
Read STOP bit in ICSR register (14) STOP = 1 ? Yes ICCR1 register TRS bit 0 MST bit 0 (15) ICSR register TDRE bit 0 End
No
Figure 16.46
Example of Register Setting in Master Transmit Mode (I2C bus Interface Mode) Page 363 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Master receive mode ICSR register ICCR1 register ICSR register ICIER register TEND bit 0 TRS bit 0 TDRE bit 0 ACKBT bit 0 (2) (3) (1) (1) Set the TEND bit to 0 and set to master receive mode. Set the TDRE bit to 0 (1,2) (2) Set the ACKBT bit to the transmit device (1) (3) Dummy read the ICDRR register(1) (4) Wait for 1 byte to be received (5) Judge (last receive - 1) (6) Read the receive data Read RDRF bit in ICSR register (4) RDRF = 1 ? (9) Wait until the last byte is received Yes Yes Last receive -1? No Read ICDRR register (6) (5) (10) Set the STOP bit to 0 (11) Generate the stop condition (12) Wait until the stop condition is generated (13) Read the receive data of the last byte (14) Set the RCVD bit to 0 ICIER register ICCR1 register ACKBT bit 1 (7) RCVD bit 1 (8) (15) Set to slave receive mode (7) Set the ACKBT bit of the last byte and set to disable continuous receive operation (RCVD = 1)(2) (8) Read the receive data of (last byte - 1)
Dummy read in ICDRR register
No
Read ICDRR register Read RDRF bit in ICSR register
No
(9) RDRF = 1 ? Yes
ICSR register ICCR2 register
STOP bit 0 SCP bit 0 BBSY bit 0
(10) (11)
Read STOP bit in ICSR register
No
(12) STOP = 1 ? Yes
Read ICDRR register ICCR1 register ICCR1 register RCVD bit 0 MST bit 0 End
(13) (14) (15)
NOTES: 1. Do not generate the interrupt while processing steps (1) to (3). 2. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to process of step (7). Processing step (8) is dummy read of the ICDRR register.
Figure 16.47
Example of Register Setting in Master Receive Mode (I2C bus Interface Mode) Page 364 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Slave transmit mode ICSR register AAS bit 0 (1) Set the AAS bit to 0 (1) (2) Set the transmit data (except the last byte) Write transmit data to ICDRT register Read TDRE bit in ICSR register (2) (3) Wait until the ICRDT register is empty (4) Set the transmit data of the last byte (5) Wait until the last byte is transmitted No TDRE = 1 ? Yes No Last byte ? (4) Yes Write transmit data to ICDRT register Read TEND bit in ICSR register (3) (6) Set the TEND bit to 0 (7) Set to slave receive mode (8) Dummy read the ICDRR register to release the SCL signal (9) Set the TDRE bit to 0
No
TEND = 1 ? Yes TEND bit 0 TRS bit 0
(5)
ICSR register ICCR1 register
(6) (7) (8) (9)
Dummy read in ICDRR register ICSR register TDRE bit 0 End
Figure 16.48
Example of Register Setting in Slave Transmit Mode (I2C bus Interface Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 365 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Slave receive mode ICSR register AAS bit 0 (1) (2) (3) Dummy read the ICDRR register Dummy read ICDRR register (3) (4) Wait until 1 byte is received (5) Judge (last receive - 1) Read RDRF bit in ICSR register (6) Read the receive data No (4) RDRF = 1 ? (8) Read the receive data of (last byte - 1) Yes (9) Wait until the last byte is received Last receive -1? No Read ICDRR register (6) Yes (5) (10) Read the receive data of the last byte (7) Set the ACKBT bit of the last byte(1) (1) Set the AAS bit to 0 (1) (2) Set the ACKBT bit to the transmit device
ICIER register ACKBT bit 0
ICIER register
ACKBT bit 1
(7) (8)
Read ICDRR register Read RDRF bit in ICSR register
No
(9) RDRF = 1 ? Yes
Read ICDRR register End
(10)
NOTE: 1. When receiving 1 byte, skip steps (2) to (6) after (1) and jump to processing step (7). Processing step (8) is dummy read of the ICDRR register.
Figure 16.49
Example of Register Setting in Slave Receive Mode (I2C bus Interface Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 366 of 485
R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
16.3.8
Notes on I2C bus Interface
Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
16.3.8.1
Multimaster Operation
The following actions must be performed to use the I2C bus interface in multimaster operation. * Transfer rate Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to 223 kbps (= 400/1.18) or more. * Bits MST and TRS in the ICCR1 register setting (a) Use the MOV instruction to set bits MST and TRS. (b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0 again.
16.3.8.2
Master Receive Mode
Either of the following actions must be performed to use the I2C bus interface in master receive mode. (a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register before the rising edge of the 8th clock. (b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive operation) to perform 1-byte communications.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 367 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
17. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
17.1
Features
The hardware LIN has the features listed below. Figure 17.1 shows a Block Diagram of Hardware LIN. Master mode * Generates Synch Break * Detects bus collision Slave mode * Detects Synch Break * Measures Synch Field * Controls Synch Break and Synch Field signal inputs to UART0 * Detects bus collision NOTE: 1. The WakeUp function is detected by INT1.
Hardware LIN
RXD0 pin Synch Field control circuit TIOSEL = 0 RXD data LSTART bit SBE bit LINE bit RXD0 input control circuit TIOSEL = 1 Interrupt control circuit UART0 BCIE, SBIE, and SFIE bits UART0 transfer clock UART0 TE bit Timer RA output pulse MST bit TXD0 pin LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register TIOSEL: Bit in TRAIOC register TE: Bit in U0C1 register UART0 TXD data Timer RA underflow signal Timer RA interrupt Timer RA
Bus collision detection circuit
Figure 17.1
Block Diagram of Hardware LIN
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 368 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
17.2
Input/Output Pins
The pin configuration of the hardware LIN is listed in Table 17.1. Table 17.1 Pin Configuration Abbreviation RXD0 TXD0 Input/Output Input Output Function Receive data input pin of the hardware LIN Transmit data output pin of the hardware LIN
Name Receive data input Transmit data output
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 369 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
17.3
Register Configuration
The hardware LIN contains the registers listed below. These registers are detailed in Figures 17.2 and 17.3. * LIN Control Register (LINCR) * LIN Status Register (LINST)
LIN Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol LINCR Bit Symbol
SFIE
Address 0106h Bit Name Synch Field measurementcompleted interrupt enable bit
After Reset 00h Function 0 : Disables Synch Field measurementcompleted interrupt 1 : Enables Synch Field measurementcompleted interrupt
RW
RW
SBIE BCIE RXDSF
Synch Break detection interrupt 0 : Disables Synch Break detection interrupt enable bit 1 : Enables Synch Break detection interrupt Bus collision detection interrupt 0 : Disables bus collision detection interrupt enable bit 1 : Enables bus collision detection interrupt RXD0 input status flag Synch Break detection start bit(1) 0 : RXD0 input enabled 1 : RXD0 input disabled When this bit is set to 1, timer RA input is enabled and RXD0 input is disabled. When read, the content is 0.
RW RW RO
LSTART
RW
SBE
RXD0 input unmasking timing 0 : Unmasked after Synch Break is detected select bit (effective only in slave 1 : Unmasked after Synch Field measurement mode) is completed LIN operation mode setting bit(2) 0 : Slave mode (Synch Break detection circuit actuated) 1 : Master mode (timer RA output OR'ed w ith TXD0) 0 : Causes LIN to stop 1 : Causes LIN to start operating(3)
RW
MST
RW
LINE
LIN operation start bit
RW
NOTES: 1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts. 2. Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0). 3. Inputs to timer RA and UART0 are prohibited immediately after this bit is set to 1. (Refer to Figure 17.5 Exam ple of Header Field Transm ission Flow chart (1) and Figure 17.9 Exam ple of Header Field Reception Flow chart (2).)
Figure 17.2
LINCR Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 370 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
LIN Status Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol LINST Bit Symbol SFDCT SBDCT BCDCT
Address 0107h Bit Name Synch Field measurementcompleted flag Synch Break detection flag Bus collision detection flag SFDCT bit clear bit
After Reset 00h Function 1 show s Synch Field measurement completed. 1 show s Synch Break detected or Synch Break generation completed. 1 show s Bus collision detected When this bit is set to 1, the SFDCT bit is set to 0. When read, the content is 0. When this bit is set to 1, the SBDCT bit is set to 0. When read, the content is 0. When this bit is set to 1, the BCDCT bit is set to 0. When read, the content is 0.
RW RO RO RO
B0CLR SBDCT bit clear bit B1CLR BCDCT bit clear bit B2CLR -- (b7-b6)
RW
RW
RW
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
--
Figure 17.3
LINST Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 371 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
17.4 17.4.1
Functional Description Master Mode
Figure 17.4 shows typical operation of the hardware LIN when transmitting a header field in master mode. Figures 17.5 and 17.6 show a flowchart of the procedure for transmitting a header field. When transmitting a header field, the hardware LIN operates as described below. (1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware LIN outputs "L" level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for timer RA. (2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the LINCR register is set to 1, it generates a timer RA interrupt. (3) The hardware LIN transmits 55h via UART0. (4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h. (5) The hardware LIN performs communication for a response field after it finishes sending the ID field.
Synch Break
Synch Field
IDENTIFIER
TXD0 pin
1 0 1 0 1 0 (1) (2) (3) Set by writing 1 to the B1CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program
SBDCT flag in the LINST register IR bit in the TRAIC register
(4)
(5)
The above applies under the following conditions: LINE = 1, MST = 1, SBIE = 1
Figure 17.4
Typical Operation when Sending a Header Field
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 372 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
Timer RA Set to timer mode Bits TMOD0 to TMOD2 in TRAMR register 000b Timer RA Set the pulse output level from low to start TEDGSEL bit in TRAIOC register 1 Timer RA Set the INT1/TRAIO pin to P1_5 TIOSEL bit in TRAIOC register 1 Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register UART0 Set to transmit/receive mode (Transfer data length: 8 bits, Internal clock, 1 stop bit, Parity disabled) U0MR register Set the BRG count source (f1, f8, f32) U0C0CLK0 to 1 bit Set the bit rate U0BRG register For the hardware LIN function, set the TIOSEL bit in the TRAIOC register to 1.
Set the count source and registers TRA and TRAPRE as suitable for the Synch Break period.
UART0
UART0
Set the BRG count source and U0BRG register as appropriate for the bit rate.
Hardware LIN Set the LIN operation to stop LINCR register LINE bit 0 Hardware LIN Set to master mode MST bit in LINCR register 1 Hardware LIN Set the LIN operation to start LINE bit in LINCR register 1 Hardware LIN Set the register to enable interrupts (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in LINCR register
Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in LINST register 1
During master mode, the Synch Field measurementcompleted interrupt cannot be used.
A
Figure 17.5 Example of Header Field Transmission Flowchart (1) Page 373 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
17. Hardware LIN
A
Timer RA Set the timer to start counting TSTART bit in TRACR register 1 Timer RA Read the count status flag TCSTF flag in TRACR register
Timer RA generates Synch Break. If registers TRAPRE and TRA for timer RA do not need to be read or the register settings do not need to be changed after writing 1 to the TSTART bit, the procedure for reading TCSTF flag = 1 can be omitted. Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1.
The timer RA interrupt may be used to terminate generation of Synch Break. One to two cycles of the CPU clock are required after Synch Break generation completes before the SBDCT flag is set to 1.
TCSTF = 1 ?
NO
YES
Hardware LIN Read the Synch Break detection flag SBDCT flag in LINST register
SBDCT = 1 ?
NO
YES
Timer RA Set the timer to stop counting TSTART bit in TRACR register 0
Timer RA Read the count status flag TCSTF flag in TRACR register
TCSTF = 0 ? YES
UART0 Communication via UART0 TE bit in U0C1 register 1 U0TB register 0055h
NO
After timer RA Synch Break is generated, the timer should be made to stop counting. If registers TRAPRE and TRA for timer RA do not need to be read or the register settings do not need to be changed after writing 0 to the TSTART bit, the procedure for reading TCSTF flag = 0 can be omitted. Zero to one cycle of the timer RA count source is required after timer RA stops counting before the TCSTF flag is set to 0.
Transmit the Synch Field.
UART0 Communication via UART0 U0TB register ID field
Transmit the ID field.
Figure 17.6
Example of Header Field Transmission Flowchart (2)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 374 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
17.4.2
Slave Mode
Figure 17.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure 17.8 through Figure 17.10 show a flowchart for the procedure for receiving a header field. When receiving a header field, the hardware LIN operates as described below. (1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware LIN. (2) When "L" level is input for a duration equal to or greater than the period set in timer RA, the hardware LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1. Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA interrupt. Then it goes to Synch Field measurement. (3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly. (4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt. (5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA and set to UART0 and registers TRAPRE and TRA of timer RA again. (6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.
Synch Break
Synch Field
IDENTIFIER
RXD0 pin
1 0 1 0 1 0 1 0 1 0 1 0 (1) (2) (3)
RXD0 input for UART0 RXDSF flag in the LINCR register SBDCT flag in the LINST register SFDCT flag in the LINST register IR bit in the TRAIC register
Set by writing 1 to the LSTART bit in the LINCR register Set by writing 1 to the B1CLR bit in the LINST register Measure this period
Cleared to 0 when Synch Field measurement finishes
Set by writing 1 to the B0CLR bit in the LINST register
Cleared to 0 upon acceptance of interrupt request or by a program
(4)
(5)
(6)
The above applies under the following conditions: LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
Figure 17.7
Typical Operation when Receiving a Header Field
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 375 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
Timer RA Set to pulse width measurement mode Bits TMOD0 to TMOD2 in the TRAMR register 011b Timer RA Set the pulse width measurement level low TEDGSEL bit in the TRAIOC register 0 Timer RA Set the INT1/TRAIO pin to P1_5 TIOSEL bit in the TRAIOC register 1 Timer RA Set the count source (f1, f2, f8, fOCO) Bits TCK0 to TCK2 in the TRAMR register Timer RA Set the Synch Break width TRAPRE register TRA register Hardware LIN Set the LIN operation to stop LINE bit in the LINCR register 0 Hardware LIN Set to slave mode MST bit in the LINCR register 0 Hardware LIN Set the LIN operation to start LINE bit in the LINCR register 1 Hardware LIN Set the RXD0 input unmasking timing (After Synch Break detection, or after Synch Field measurement) SBE bit in the LINCR register Select the timing at which to unmask the RXD0 input for UART0. If the RXD0 input is chosen to be unmasked after detection of Synch Break, the Synch Field signal is also input to UART0. Set the count source and registers TRA and TRAPRE as appropriate for the Synch Break period. For the hardware LIN function, set the TIOSEL bit in the TRAIOC register to 1.
Hardware LIN Set the register to enable interrupts (Bus collision detection, Synch Break detection, Synch Field measurement) Bits BCIE, SBIE, SFIE in the LINCR register
A
Figure 17.8
Example of Header Field Reception Flowchart (1)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 376 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
A
Hardware LIN Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in the LINST register 1
Timer RA Set to start a pulse width measurement TSTART bit in the TRACR register 1 Timer RA Read the count status flag TCSTF flag in the TRACR register
Timer RA waits until the timer starts counting.
TCSTF = 1 ? YES
NO
Hardware LIN Set to start Synch Break detection LSTART bit in the LINCR register 1
Hardware LIN Read the RXD0 input status flag RXDSF flag in the LINCR register
RXDSF = 1 ? YES
NO
Hardware LIN Read the Synch Break detection flag SBDCT flag in the LINST register
SBDCT = 1 ? YES
NO
B
Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1. Hardware LIN waits until the RXD0 input for UART0 is masked. Do not apply "L" level to the RXD pin until the RXDSF flag reads 1 after writing 1 to the LSTART bit. This is because the signal applied during this time is input directly to UART0. One to two cycles of the CPU clock and zero to one cycle of the timer RA count source are required after the LSTART bit is set to 1 before the RXDSF flag is set to 1. After this, input to timer RA and UART0 is enabled. Hardware LIN detects a Synch Break. The interrupt of the timer RA may be used. When Synch Break is detected, timer RA is reloaded with the initially set count value. Even if the duration of the input "L" level is shorter than the set period, timer RA is reloaded with the initially set count value and waits until the next "L" level is input. One to two cycles of the CPU clock are required after Synch Break detection before the SBDCT flag is set to 1. When the SBE bit in the LINCR register is set to 0 (unmasked after Synch Break is detected), timer RA can be used in timer mode after the SBDCT flag in the LINST register is set to 1 and the RXDSF flag is set to 0.
Figure 17.9
Example of Header Field Reception Flowchart (2)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 377 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
B
YES Hardware LIN Read the Synch Field measurementcompleted flag SFDCT flag in the LINST register NO
SFDCT = 1 ? YES
Hardware LIN measures the Synch Field. The interrupt of timer RA may be used (the SBDCT flag is set when the timer RA counter underflows upon reaching the terminal count). When the SBE bit in the LINCR register is set to 1 (unmasked after Synch Field measurement is completed), timer RA may be used in timer mode after the SFDCT bit in the LINST register is set to 1.
UART0 Set the UART0 communication rate U0BRG register Timer RA Set the Synch Break width again TRAPRE register TRA register UART0 Communication via UART0 Clock asynchronous serial interface (UART) mode Transmit ID field
Set a communication rate based on the Synch Field measurement result.
Communication via UART0 (The SBDCT flag is set when the timer RA counter underflows upon reaching the terminal count.)
Figure 17.10
Example of Header Field Reception Flowchart (3)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 378 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
17.4.3
Bus Collision Detection Function
The bus collision detection function can be used when UART0 is enabled for transmission (TE bit in the U0C1 register = 1). Figure 17.11 shows the Typical Operation when a Bus Collision is Detected.
TXD0 pin
1 0 1 0 1 0 Set to 1 by a program
RXD0 pin
Transfer clock
LINE bit in the LINCR register TE bit in the U0C1 register BCDCT flag in the LINST register
1 0 Set to 1 by a program 1 0 1 0 Set by writing 1 to the B2CLR bit in the LINST register Cleared to 0 upon acceptance of interrupt request or by a program
IR bit in the TRAIC register
1 0
Figure 17.11
Typical Operation when a Bus Collision is Detected
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 379 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
17.4.4
Hardware LIN End Processing
Figure 17.12 shows an Example of Hardware LIN Communication Completion Flowchart. Use the following timing for hardware LIN end processing: * If the hardware bus collision detection function is used Perform hardware LIN end processing after checksum transmission completes. * If the bus collision detection function is not used Perform hardware LIN end processing after header field transmission and reception complete.
Timer RA
Set the timer to stop counting TSTART bit in TRACR register 0 Read the count status flag TCSTF flag in TRACR register NO
Set the timer to stop counting. Zero to one cycle of the timer RA count source is required after timer RA starts counting before the TCSTF flag is set to 1.
Timer RA
TCSTF = 0 ? YES UART0 Complete transmission via UART0
When the bus collision detection function is not used, end processing for the UART0 transmission is not required.
Hardware LIN
Clear the status flags (Bus collision detection, Synch Break detection, Synch Field measurement) Bits B2CLR, B1CLR, B0CLR in the LINST register 1 Set the LIN operation to stop LINE bit in the LINCR register 0
After clearing hardware LIN status flag, stop the hardware LIN operation.
Hardware LIN
Figure 17.12
Example of Hardware LIN Communication Completion Flowchart
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 380 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
17.5
Interrupt Requests
There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break generation completed, Synch Field measurement, and bus collision detection. These interrupts are shared with timer RA. Table 17.2 lists the Interrupt Requests of Hardware LIN. Table 17.2 Interrupt Requests of Hardware LIN Status Flag SBDCT Cause of Interrupt Generated when timer RA has underflowed after measuring the "L" level duration of RXD0 input, or when a "L" level is input for a duration longer than the Synch Break period during communication. Generated when "L" level output to TXD0 for the duration set by timer RA completes. SFDCT BCDCT Generated when measurement for 6 bits of the Synch Field by timer RA is completed. Generated when the RXD0 input and TXD0 output values differed at data latch timing while UART0 is enabled for transmission.
Interrupt Request Synch Break detection
Synch Break generation completed Synch Field measurement Bus collision detection
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 381 of 485
R8C/24 Group, R8C/25 Group
17. Hardware LIN
17.6
Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 382 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
18. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling amplifier. The analog input shares pins P0_0 to P0_7, and P1_0 to P1_3. Therefore, when using these pins, ensure that the corresponding port direction bits are set to 0 (input mode). When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected) so that no current will flow from the VREF pin into the resistor ladder. This helps to reduce the power consumption of the chip. The result of A/D conversion is stored in the AD register. Table 18.1 lists the Performance of A/D converter. Figure 18.1 shows a Block Diagram of A/D Converter. Figures 18.2 and 18.3 show the A/D converter-related registers. Table 18.1 Performance of A/D converter Performance Successive approximation (with capacitive coupling amplifier) 0 V to AVCC 4.2 V AVCC 5.5 V f1, f2, f4, fOCO-F 2.2 V AVCC < 4.2 V f2, f4, fOCO-F 8 bits or 10 bits selectable AVCC = Vref = 5 V, AD = 10 MHz * 8-bit resolution 2 LSB * 10-bit resolution 3 LSB AVCC = Vref = 3.3 V, AD = 10 MHz * 8-bit resolution 2 LSB * 10-bit resolution 5 LSB AVCC = Vref = 2.2 V, AD = 5 MHz * 8-bit resolution 2 LSB * 10-bit resolution 5 LSB One-shot and repeat(3) 12 pins (AN0 to AN11) * Software trigger Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts) * Capture Timer RD interrupt request is generated while the ADST bit is set to 1 * Without sample and hold function 8-bit resolution: 49AD cycles, 10-bit resolution: 59AD cycles * With sample and hold function 8-bit resolution: 28AD cycles, 10-bit resolution: 33AD cycles
Item A/D conversion method Analog input voltage(1) Operating clock AD(2) Resolution Absolute accuracy
Operating mode Analog input pin A/D conversion start condition
Conversion rate per pin
NOTES: 1. The analog input voltage does not depend on use of a sample and hold function. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. 2. When 2.7 V AVCC 5.5 V, the frequency of AD must be 10 MHz or below. When 2.2 V AVCC < 2.7 V, the frequency of AD must be 5 MHz or below. Without a sample and hold function, the AD frequency should be 250 kHz or above. With a sample and hold function, the AD frequency should be 1 MHz or above. 3. In repeat mode, only 8-bit mode can be used.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 383 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
fOCO-F f1
CKS0 = 1 A/D conversion rate selection CKS1 = 1 CKS0 = 0 CKS0 = 1
f2 f4
CKS0 = 0 VCUT = 0 CKS1 = 0
AD
AVSS VREF
VCUT = 1
Resistor ladder
Successive conversion register
Software trigger Timer RD interrupt request
ADCAP = 0
ADCON0
Trigger
ADCAP = 1 Vcom
AD register
Decoder Comparator
Data bus
VIN
P0_7/AN0 P0_6/AN1 P0_5/AN2 P0_4/AN3 P0_3/AN4 P0_2/AN5 P0_1/AN6 P0_0/AN7
CH2 to CH2 to CH2 to CH2 to CH2 to CH2 to CH2 to CH2 to
CH0 = 000b CH0 = 001b CH0 = 010b CH0 = 011b CH0 = 100b CH0 = 101b CH0 = 110b CH0 = 111b
ADGSEL0 = 0
ADGSEL0 = 1
P1_0/AN8 P1_1/AN9 P1_2/AN10 P1_3/AN11
CH2 to CH0 = 100b CH2 to CH0 = 101b CH2 to CH0 = 110b CH2 to CH0 = 111b
CH0 to CH2, ADGSEL0, CKS0: Bits in ADCON0 register CKS1, VCUT: Bits in ADCON1 register
Figure 18.1
Block Diagram of A/D Converter
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 384 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD ADGSEL0
Address 00D6h Bit Name Analog input pin select bits (Note 4)
After Reset 00h Function
RW RW RW RW
A/D operating mode select 0 : One-shot mode bit(2) 1 : Repeat mode A/D input group select bit
(4)
RW RW
0 : Selects port P0 group (AN0 to AN7) 1 : Selects port P1 group (AN8 to AN11) 0 : Starts at softw are trigger (ADST bit) 1 : Starts at timer RD (complementary PWM mode) 0 : Stops A/D conversion 1 : Starts A/D conversion [When CKS1 in ADCON1 register = 0] 0 : Selects f4 1 : Selects f2 [When CKS1 in ADCON1 register = 1] 0 : Selects f1(3) 1 : Selects fOCO-F
ADCAP
A/D conversion automatic start bit A/D conversion start flag Frequency select bit 0
RW
ADST
RW
CKS0
RW
NOTES: 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined. 2. When changing A/D operating mode, set the analog input pin again. 3. Set oAD frequency to 10 MHz or below . 4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit. CH2 to CH0 000b 001b 010b 011b 100b 101b 110b 111b ADGSEL0 = 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADGSEL0 = 1 Do not set.
AN8 AN9 AN10 AN11
Figure 18.2
ADCON0 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 385 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
00
000
Symbol Address 00D7h ADCON1 Bit Symbol Bit Name -- Reserved bits (b2-b0) BITS CKS1 VCUT -- (b6-b7) 8/10-bit mode select bit(2) Frequency select bit 1 Vref connect bit(3) Reserved bits
After Reset 00h Function Set to 0. 0 : 8-bit mode 1 : 10-bit mode Refer to the description of the CKS0 bit in the ADCON0 register function 0 : Vref not connected 1 : Vref connected Set to 0.
RW RW RW RW RW RW
NOTES: 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined. 2. Set the BITS bit to 0 (8-bit mode) in repeat mode. 3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 s or more before starting A/D conversion.
A/D Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol ADCON2 Bit Symbol SMP -- (b3-b1) -- (b7-b4)
Address 00D4h Bit Name A/D conversion method select bit Reserved bits
After Reset 00h Function 0 : Without sample and hold 1 : With sample and hold Set to 0.
RW RW RW --
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
NOTE: 1. If the ADCON2 register is rew ritten during A/D conversion, the conversion result is undefined.
A/D Register
(b15) b7 (b8) b0 b7 b0
Symbol AD Function When BITS bit in ADCON1 register is set to 1 (10-bit mode). 8 low -order bits in A/D conversion result 2 high-order bits in A/D conversion result Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Address 00C1h-00C0h
After Reset Undefined RW RW RO RO --
When BITS bit in ADCON1 register is set to 0 (8-bit mode). A/D conversion result When read, the content is undefined.
Figure 18.3
Registers ADCON1, ADCON2, and AD Page 386 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
18. A/D Converter
18.1
One-Shot Mode
In one-shot mode, the input voltage of one selected pin is A/D converted once. Table 18.2 lists the One-Shot Mode Specifications. Figures 18.4 and 18.5 show Registers ADCON0 and ADCON1 in One-Shot Mode. Table 18.2 One-Shot Mode Specifications Item
Specification Function The input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is A/D converted once Start condition * When the ADCAP bit is set to 0 (software trigger): Set the ADST bit to 1 (A/D conversion starts) * When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM mode): A compare match between registers TRD0 and TRDGRA0 or a TRD1 underflow is generated while the ADST bit is set to 1 Stop condition * A/D conversion completes (when the ADCAP bit is set to 0 (software trigger) ADST bit is set to 0) * Set the ADST bit to 0 Interrupt request generation A/D conversion completes timing Input pin Select one of AN0 to AN11 Reading of A/D conversion Read AD register result
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 387 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD ADGSEL0
Address 00D6h Bit Name Analog input pin select bits (Note 4)
After Reset 00h Function
RW RW RW RW
A/D operating mode select 0 : One-shot mode bit(2) A/D input group select bit
(4)
RW RW
0 : Selects port P0 group (AN0 to AN7) 1 : Selects port P1 group (AN8 to AN11) 0 : Starts at softw are trigger (ADST bit) 1 : Starts at timer RD (complementary PWM mode) 0 : Stops A/D conversion 1 : Starts A/D conversion [When CKS1 in ADCON1 register = 0] 0 : Selects f4 1 : Selects f2 [When CKS1 in ADCON1 register = 1] 0 : Selects f1(3) 1 : Selects fOCO-F
ADCAP
A/D conversion automatic start bit A/D conversion start flag Frequency select bit 0
RW
ADST
RW
CKS0
RW
NOTES: 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined. 2. After changing the A/D operating mode, select the analog input pin again. 3. Set oAD frequency to 10 MHz or below . 4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit. CH2 to CH0 000b 001b 010b 011b 100b 101b 110b 111b ADGSEL0 = 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADGSEL0 = 1 Do not set.
AN8 AN9 AN10 AN11
Figure 18.4
ADCON0 Register in One-Shot Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 388 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
001
000
Symbol Address 00D7h ADCON1 Bit Symbol Bit Name -- Reserved bits (b2-b0) BITS CKS1 VCUT -- (b6-b7) 8/10-bit mode select bit Frequency select bit 1 Vref connect bit Reserved bits
(2)
After Reset 00h Function Set to 0. 0 : 8-bit mode 1 : 10-bit mode Refer to the description of the CKS0 bit in the ADCON0 register function 1 : Vref connected Set to 0.
RW RW RW RW RW RW
NOTES: 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined. 2. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 s or more before starting A/D conversion.
Figure 18.5
ADCON1 Register in One-Shot Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 389 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
18.2
Repeat Mode
In repeat mode, the input voltage of one selected pin is A/D converted repeatedly. Table 18.3 lists the Repeat Mode Specifications. Figures 18.6 and 18.7 show Registers ADCON0 and ADCON1 in Repeat Mode. Table 18.3 Repeat Mode Specifications Item
Specification Function The Input voltage of one pin selected by bits CH2 to CH0 and ADGSEL0 is A/D converted repeatedly Start conditions * When the ADCAP bit is set to 0 (software trigger): Set the ADST bit to 1 (A/D conversion starts) * When the ADCAP bit is set to 1 (starts in timer RD (complementary PWM mode)): A compare match between registers TRD0 and TRDGRA0 or a TRD1 underflow is generated while the ADST bit is set to 1 Stop condition Set the ADST bit to 0 Interrupt request generation Not generated timing Input pin Select one of AN0 to AN11 Reading of result of A/D Read AD register converter
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 390 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
A/D Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol ADCON0 Bit Symbol CH0 CH1 CH2 MD ADGSEL0
Address 00D6h Bit Name Analog input pin select bits (Note 4)
After Reset 00h Function
RW RW RW RW
A/D operating mode select 1 : Repeat mode bit(2) A/D input group select bit(4) 0 : Selects port P0 group (AN0 to AN7) 1 : Selects port P1 group (AN8 to AN11) A/D conversion automatic start bit A/D conversion start flag Frequency select bit 0 0 : Starts at softw are trigger (ADST bit) 1 : Starts at timer RD (complementary PWM mode) 0 : Stops A/D conversion 1 : Starts A/D conversion [When CKS1 in ADCON1 register = 0] 0 : Selects f4 1 : Selects f2 [When CKS1 in ADCON1 register = 1] 0 : Selects f1(3) 1 : Do not set.
RW RW
ADCAP
RW
ADST
RW
CKS0
RW
NOTES: 1. If the ADCON0 register is rew ritten during A/D conversion, the conversion result is undefined. 2. After changing A/D operation mode, select the analog input pin again. 3. Set oAD frequency to 10 MHz or below . 4. The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit. CH2 to CH0 000b 001b 010b 011b 100b 101b 110b 111b ADGSEL0 = 0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADGSEL0 = 1 Do not set.
AN8 AN9 AN10 AN11
Figure 18.6
ADCON0 Register in Repeat Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 391 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
A/D Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
001
0000
Symbol Address 00D7h ADCON1 Bit Symbol Bit Name -- Reserved bits (b2-b0) BITS CKS1 VCUT -- (b6-b7) 8/10-bit mode select bit(2) Frequency select bit 1 Vref connect bit(3) Reserved bits
After Reset 00h Function Set to 0. 0 : 8-bit mode Refer to the description of the CKS0 bit in the ADCON0 register function 1 : Vref connected Set to 0.
RW RW RW RW RW RW
NOTES: 1. If the ADCON1 register is rew ritten during A/D conversion, the conversion result is undefined. 2. Set the BITS bit to 0 (8-bit mode) in repeat mode. 3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 s or more before starting A/D conversion.
Figure 18.7
ADCON1 Register in Repeat Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 392 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
18.3
Sample and Hold
When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate per pin increases. The sample and hold function is available in all operating modes. Start A/D conversion after selecting whether the sample and hold circuit is to be used or not. Figure 18.8 shows a Timing Diagram of A/D Conversion.
Sample and hold disabled
Conversion time of 1st bit Sampling time 4o AD cycles
2nd bit
Comparison Sampling time Comparison Sampling time Comparison 2.5o AD cycles 2.5o AD cycles time time time
* Repeat until conversion ends
Sample and hold enabled
Conversion time of 1st bit Sampling time 4o AD cycles Comparison time
2nd bit Comparison Comparison Comparison time time time
* Repeat until conversion ends
Figure 18.8
Timing Diagram of A/D Conversion
18.4
A/D Conversion Cycles
Figure 18.9 shows the A/D Conversion Cycles.
Conversion time at the 1st bit
Conversion time at the 2nd bit and the follows
End process
A/D Conversion Mode Without Sample & Hold Without Sample & Hold With Sample & Hold With Sample & Hold 8 bits 10 bits 8 bits 10 bits
Conversion Time 49AD 59AD 28AD 33AD
Sampling Time 4AD 4AD 4AD 4AD
Comparison Time 2.0AD 2.0AD 2.5AD 2.5AD
Sampling Time 2.5AD 2.5AD 0.0AD 0.0AD
Comparison End process Time 2.5AD 2.5AD 2.5AD 2.5AD 8.0AD 8.0AD 4.0AD 4.0AD
Figure 18.9
A/D Conversion Cycles
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 393 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
18.5
Internal Equivalent Circuit of Analog Input
Figure 18.10 shows the Internal Equivalent Circuit of Analog Input.
VCC VCC VSS AVCC Parasitic Diode AN0 ON Resistor Approx. 2k Wiring Resistor Approx. 0.2k SW1 Parasitic Diode ON Resistor Approx. 0.6k Analog Input Voltage SW2 VIN ON Resistor Approx. 5k SW3
C = Approx.1.5pF
AMP
Sampling Control Signal VSS
SW4
i = 12
i Ladder-type Switches
i Ladder-type Wiring Resistors AVSS
Chopper-type Amplifier
ON Resistor Approx. 2k Wiring Resistor Approx. 0.2k AN11 SW1
b4 b2 b1 b0 A/D Control Register 0
VREF
Reference Control Signal
A/D Successive Conversion Register
Vref
Resistor ladder
AVSS
SW5
ON Resistor Approx. 0.6k f
Comparison voltage A/D Conversion Interrupt Request
Comparison reference voltage (Vref) generator
Sampling C parison om C onnect to
SW1 conducts only on the ports selected for analog input. SW2 and SW3 are open when A/D conversion is not in progress; their status varies as shown by the waveforms in the diagrams on the left.
Control signal for SW2
C onnect to
C onnect to
SW4 conducts only when A/D conversion is not in progress. SW5 conducts when compare operation is in progress.
C onnect to
Control signal for SW3
NOTE: 1. Use only as a standard for designing this data. Mass production may cause some changes in device characteristics.
Figure 18.10
Internal Equivalent Circuit of Analog Input
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 394 of 485
R8C/24 Group, R8C/25 Group
18. A/D Converter
18.6
Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 18.11 has to be completed within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X, and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). 1 - -------------------------C ( R0 + R ) VC = VIN 1 - e t
VC is generally
And when t = T,
X X VC = VIN - --- VIN = VIN 1 - --- Y Y 1 - --------------------------T C ( R0 + R ) = X e --Y 1 - -------------------------- T = ln X --C ( R0 + R ) Y
Hence,
T R0 = - ------------------- - R X C * ln --Y
Figure 18.11 shows the Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision added to 0.1LSB. When f(XIN) = 10 MHz, T = 0.25 s in the A/D conversion mode without sample & hold. Output impedance R0 for sufficiently charging capacitor C within time T is determined as follows. T = 0.25 s, R = 2.8 k, C = 6.0 pF, X = 0.1, and Y = 1024. Hence,
3 3 0.25 x 10 - 6 R0 = - -------------------------------------------------- - 2.8 x10 1.7 x10 0.1 6.0 x 10 - 12 * ln ----------1024
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less, is approximately 1.7 k. maximum.
MCU Sensor equivalent circuit R0 VIN C (6.0 pF) VC R (2.8 k)
NOTE: 1. The capacity of the terminal is assumed to be 4.5 pF.
Figure 18.11
Analog Input Pin and External Sensor Equivalent Circuit Page 395 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
18. A/D Converter
18.7
Notes on A/D Converter
* Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs). * When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF connected), wait for at least 1 s before starting the A/D conversion. * After changing the A/D operating mode, select an analog input pin again. * When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D conversion is completed. * When using the repeat mode, select the frequency of the A/D converter operating clock AD or more for the CPU clock during A/D conversion. Do not select the fOCO-F for the AD. * If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register. * Connect 0.1 F capacitor between the P4_2/VREF pin and AVSS pin. * Do not enter stop mode during A/D conversion. * Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in wait mode) during A/D conversion.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 396 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19. Flash Memory
19.1 Overview
In the flash memory, rewrite operations to the flash memory can be performed in three modes: CPU rewrite, standard serial I/O, and parallel I/O. Table 19.1 lists the Flash Memory Performance (refer to Table 1.1 Functions and Specifications for R8C/24 Group and Table 1.2 Functions and Specifications for R8C/25 Group for items not listed in Table 19.1). Table 19.1 Flash Memory Performance
Specification 3 modes (CPU rewrite, standard serial I/O, and parallel I/O) Refer to Figure 19.1 and Figure 19.2 Byte unit Block erase Program and erase control by software command
Item Flash memory operating mode Division of erase block Programming method Erase method
Programming and erasure control method(3) Rewrite control method
Rewrite control for blocks 0 and 1 by FMR02 bit in FMR0 register Rewrite control for block 0 by FMR15 bit and Block 1 by FMR16 bit in FMR1 register Number of commands 5 commands Programming and Blocks 0 and 1 (program R8C/24 Group: 100 times; R8C/25 Group: 1,000 times ROM) erasure endurance(1) Blocks A and B (data 10,000 times flash)(2) ID code check function Standard serial I/O mode supported ROM code protect Parallel I/O mode supported NOTES: 1. Definition of programming and erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When performing 100 or more rewrites, the actual erase count can be reduced by executing programming operations in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 2. Blocks A and B are implemented only in the R8C/25 group. 3. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V.
Table 19.2
Flash Memory Rewrite Modes Standard Serial I/O Mode User ROM area is rewritten by executing User ROM area is rewritten by a software commands from the CPU. dedicated serial EW0 mode: Rewritable in the RAM EW1 mode: Rewritable in flash memory programmer. User ROM area User ROM area CPU Rewrite Mode Boot mode Serial programmer Parallel I/O Mode User ROM area is rewritten by a dedicated parallel programmer. User ROM area Parallel I/O mode Parallel programmer
Flash memory Rewrite mode Function
Areas which can be rewritten Operating mode Single chip mode ROM Programmer None
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 397 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.2
Memory Map
The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 19.1 shows the Flash Memory Block Diagram for R8C/24 Group. Figure 19.2 shows a Flash Memory Block Diagram for R8C/25 Group. The user ROM area of the R8C/25 Group contains an area (program ROM) which stores MCU operating programs and blocks A and B (data flash) each 1 Kbyte in size. The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and standard serial I/O and parallel I/O modes. When rewriting blocks 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite enabled). When the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot ROM area and the user ROM area share the same address, but have separate memory areas.
48 Kbytes ROM product
04000h
04000h
64 Kbytes ROM product
32 Kbytes ROM product
08000h
Block 1: 32 Kbytes(1)
Block 1: 32 Kbytes(1)
Block 1: 16 Kbytes
0BFFFh 0C000h
(1)
0BFFFh 0C000h
0BFFFh 0C000h
Program ROM
Block 0: 16 Kbytes(1)
0FFFFh
0FFFFh
Block 0: 16 Kbytes(1)
User ROM area
0FFFFh 10000h
User ROM area
Block 0: 32 Kbytes(1)
13FFFh
User ROM area
24 Kbytes ROM product
0A000h
Program ROM
Block 1: 8 Kbytes(1)
0BFFFh 0C000h
16 Kbytes ROM product
0C000h
Block 0: 16 Kbytes(1)
0FFFFh
Block 0: 16 Kbytes(1)
0FFFFh
0E000h
0FFFFh
8 Kbytes Boot ROM area (reserved area)(2)
User ROM area
User ROM area
NOTES: 1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode). 2. This area is for storing the boot program provided by Renesas Technology.
Figure 19.1
Flash Memory Block Diagram for R8C/24 Group
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 398 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
02400h 02BFFh
64 Kbytes ROM product 48 Kbytes ROM product 32 Kbytes ROM product 02400h 02400h Block A: 1 Kbyte Block A: 1 Kbyte Block A: 1 Kbyte
Block B: 1 Kbyte
02BFFh
Block B: 1 Kbyte
02BFFh
Block B: 1 Kbyte
Data flash
04000h
04000h
08000h
Block 1: 32 Kbytes(1)
Block 1: 16 Kbytes(1)
Block 1: 32 Kbytes(1)
0BFFFh 0C000h
0BFFFh 0C000h
0BFFFh 0C000h
Program ROM
Block 0: 16 Kbytes
0FFFFh
(1)
Block 0: 16
0FFFFh
Kbytes(1)
0FFFFh 10000h
User ROM area
User ROM area
Block 0: 32 Kbytes(1)
13FFFh
User ROM area
24 Kbytes ROM product
02400h 02BFFh
16 Kbytes ROM product
02400h 02BFFh
Block A: 1 Kbyte Block B: 1 Kbyte
Block A: 1 Kbyte Block B: 1 Kbyte
Data flash
0A000h 0BFFFh 0C000h
Block 1: 8 Kbytes(1)
0C000h
Program ROM
Block 0: 16 Kbytes(1)
0FFFFh
0FFFFh
Block 0: 16 Kbytes(1)
User ROM area
0E000h 0FFFFh
8 Kbytes Boot ROM area (reserved area)(2)
User ROM area
NOTES: 1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0 (rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU rewrite mode). 2. This area is for storing the boot program provided by Renesas Technology.
Figure 19.2
Flash Memory Block Diagram for R8C/25 Group
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 399 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.3
Functions to Prevent Rewriting of Flash Memory
Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to prevent the flash memory from being read or rewritten easily.
19.3.1
ID Code Check Function
This function is used in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the programmer and the ID codes written in the flash memory are checked to see if they match. If the ID codes do not match, the commands sent from the programmer are not acknowledged. The ID codes consist of 8 bits of data each, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh, 00FFF3h, 00FFF7h, and 00FFFBh. Write programs in which the ID codes are set at these addresses and write them to the flash memory.
Address 00FFDFh to 00FFDCh 00FFE3h to 00FFE0h 00FFE7h to 00FFE4h 00FFEBh to 00FFE8h 00FFEFh to 00FFECh 00FFF3h to 00FFF0h 00FFF7h to 00FFF4h 00FFFBh to 00FFF8h 00FFFFh to 00FFFCh
ID1 ID2
Undefined instruction vector Overflow vector BRK instruction vector
ID3 ID4 ID5 ID6 ID7 (Note 1)
Address match vector Single step vector
Oscillation stop detection/watchdog timer/voltage monitor 1 and voltage monitor 2 vector
Address break (Reserved) Reset vector 4 bytes
NOTE: 1. The OFS register is assigned to 00FFFFh. Refer to Figure 19.4 OFS Register for OFS register details.
Figure 19.3
Address for Stored ID Code
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 400 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.3.2
ROM Code Protect Function
The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the OFS register in parallel I/O mode. Figure 19.4 shows the OFS Register. The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables reading or changing the contents of the on-chip flash memory. Once ROM code protect is enabled, the content in the internal flash memory cannot be rewritten in parallel I/O mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or standard serial I/O mode.
Option Function Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
1
1
Symbol OFS Bit Symbol WDTON -- (b1) ROMCR ROMCP1 -- (b4)
Address 0FFFFh Bit Name Watchdog timer start select bit Reserved bit ROM code protect disabled bit ROM code protect bit Reserved bit Voltage detection 0 circuit start bit(2)
When Shipping FFh(3) Function 0 : Starts w atchdog timer automatically after reset 1 : Watchdog timer is inactive after reset Set to 1. 0 : ROM code protect disabled 1 : ROMCP1 enabled 0 : ROM code protect enabled 1 : ROM code protect disabled Set to 1. 0 : Voltage monitor 0 reset enabled after hardw are reset 1 : Voltage monitor 0 reset disabled after hardw are reset Set to 1. 0 : Count source protect mode enabled after reset 1 : Count source protect mode disabled after reset
RW RW RW RW RW RW
LVD0ON
RW
-- (b6)
Reserved bit
RW
Count source protect CSPROINI mode after reset select bit
RW
NOTES: 1. The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not w rite additions to the OFS register. 2. To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after reset). 3. If the block including the OFS register is erased, FFh is set to the OFS register.
Figure 19.4
OFS Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 401 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.4
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU. Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a ROM programmer. Execute the program and block erase commands only to blocks in the user ROM area. The flash module has an erase-suspend function when an interrupt request is generated during an erase operation in CPU rewrite mode. It performs an interrupt process after the erase operation is halted temporarily. During erasesuspend, the user ROM area can be read by a program. In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the flash module has a program-suspend function which performs the interrupt process after the auto-program operation is suspended. During program-suspend, the user ROM area can be read by a program. CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode). Table 19.3 lists the Differences between EW0 Mode and EW1 Mode. Table 19.3 Differences between EW0 Mode and EW1 Mode
EW0 Mode Single-chip mode User ROM area EW1 Mode Single-chip mode User ROM area
Item Operating mode Areas in which a rewrite control program can be located Areas in which a rewrite control program can be executed Areas which can be rewritten Software command restrictions
Modes after program or erase Modes after read status register CPU status during autowrite and auto-erase Flash memory status detection
Necessary to transfer to any area other Executing directly in user ROM or RAM than the flash memory (e.g., RAM) before area possible executing User ROM area User ROM area However, blocks which contain a rewrite control program are excluded(1) None * Program and block erase commands Cannot be run on any block which contains a rewrite control program * Read status register command Cannot be executed Read status register mode Read array mode Read status register mode Operating Do not execute this command
Conditions for transition to erase-suspend Conditions for transitions to program-suspend CPU clock
Hold state (I/O ports hold state before the command is executed) * Read bits FMR00, FMR06, and FMR07 Read bits FMR00, FMR06, and FMR07 in in the FMR0 register by a program the FMR0 register by a program * Execute the read status register command and read bits SR7, SR5, and SR4 in the status register. Set bits FMR40 and FMR41 in the FMR4 The FMR40 bit in the FMR4 register is set register to 1 by a program. to 1 and the interrupt request of the enabled maskable interrupt is generated Set bits FMR40 and FMR42 in the FMR4 The FMR40 bit in the FMR4 register is set register to 1 by a program. to 1 and the interrupt request of the enabled maskable interrupt is generated 5 MHz or below No restriction (on clock frequency to be used)
NOTE: 1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), rewriting block 0 is enabled by setting the FMR15 bit in the FMR1 register to 0 (rewrite enabled), and rewriting block 1 is enabled by setting the FMR16 bit to 0 (rewrite enabled).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 402 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.4.1
EW0 Mode
The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is set to 0, EW0 mode is selected. Use software commands to control program and erase operations. The FMR0 register or the status register can be used to determine when program and erase operations complete. During auto-erasure, set the FMR40 bit to 1 (erase-suspend enabled) and the FMR41 bit to 1 (request erasesuspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the user ROM area. The auto-erase operation can be restarted by setting the FMR41 bit to 0 (erase restarts). To enter program-suspend during the auto-program operation, set the FMR40 bit to 1 (suspend enabled) and the FMR42 bit to 1 (request program-suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the user ROM area. The auto-program operation can be restarted by setting the FMR42 bit to 0 (program restarts).
19.4.2
EW1 Mode
The MCU is switched to EW1 mode by setting the FMR11 bit to 1 (EW1 mode) after setting the FMR01 bit to 1 (CPU rewrite mode enabled). The FMR0 register can be used to determine when program and erase operations complete. Do not execute commands that use the read status register in EW1 mode. To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the FMR40 bit to 1 (erase-suspend enabled). The interrupt to enter erase-suspend should be in interrupt enabled status. After waiting for td(SR-SUS) after the block erase command is executed, the interrupt request is acknowledged. When an interrupt request is generated, the FMR41 bit is automatically set to 1 (requests erase-suspend) and the auto-erase operation suspends. If an auto-erase operation does not complete (FMR00 bit is 0) after an interrupt process completes, the auto-erase operation restarts by setting the FMR41 bit to 0 (erasure restarts) To enable the program-suspend function during auto-programming, execute the program command after setting the FMR40 bit to 1 (suspend enabled). The interrupt to enter program-suspend should be in interrupt enabled status. After waiting for td(SR-SUS) after the program command is executed, an interrupt request is acknowledged. When an interrupt request is generated, the FMR42 bit is automatically set to 1 (request program-suspend) and the auto-program operation suspends. When the auto-program operation does not complete (FMR00 bit is 0) after the interrupt process completes, the auto-program operation can be restarted by setting the FMR42 bit to 0 (programming restarts).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 403 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
Figure 19.5 shows the FMR0 Register. Figure 19.6 shows the FMR1 Register. Figure 19.7 shows the FMR4 Register.
19.4.2.1
FMR00 Bit
This bit indicates the operating status of the flash memory. The bits value is 0 during programming, erasure (including suspend periods), or erase-suspend mode; otherwise, it is 1.
19.4.2.2
FMR01 Bit
The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).
19.4.2.3
FMR02 Bit
Rewriting of blocks 0 and 1 does not accept program or block erase commands if the FMR02 bit is set to 0 (rewrite disabled). Rewriting of blocks 0 and 1 is controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewrite enabled).
19.4.2.4
FMSTP Bit
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1. Therefore, the FMSTP bit must be written to by a program transferred to the RAM. In the following cases, set the FMSTP bit to 1: * When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit not reset to 1 (ready)) * To provide lower consumption in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode (XIN clock stops), and low-speed clock mode (XIN clock stops). Figure 19.11 shows the handling to provide lower consumption in high-speed on-chip oscillator mode, lowspeed on-chip oscillator mode (XIN clock stops), and low-speed clock mode (XIN clock stops). Handle according to this flowchart. Note that when going to stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register does not need to be set because the power for the flash memory is automatically turned off and is turned back on again after returning from stop or wait mode.
19.4.2.5
FMR06 Bit
This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a program error occurs; otherwise, it is set to 0. For details, refer to the description in 19.4.5 Full Status Check.
19.4.2.6
FMR07 Bit
This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase error occurs; otherwise, it is set to 0. Refer to 19.4.5 Full Status Check for details.
19.4.2.7
FMR11 Bit
Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.
19.4.2.8
FMR15 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0 accepts program and block erase commands.
19.4.2.9
FMR16 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1 accepts program and block erase commands.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 404 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.4.2.10 FMR40 Bit
The suspend function is enabled by setting the FMR40 bit to 1 (enable).
19.4.2.11 FMR41 Bit
In EW0 mode, the MCU enters erase-suspend mode when the FMR41 bit is set to 1 by a program. The FMR41 bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the MCU enters erase-suspend mode. Set the FMR41 bit to 0 (erase restarts) when the auto-erase operation restarts.
19.4.2.12 FMR42 Bit
In EW0 mode, the MCU enters program-suspend mode when the FMR42 bit is set to 1 by a program. The FMR42 bit is automatically set to 1 (request program-suspend) when an interrupt request of an enabled interrupt is generated in EW1 mode, and then the MCU enters program-suspend mode. Set the FMR42 bit to 0 (program restart) when the auto-program operation restarts.
19.4.2.13 FMR43 Bit
When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress). The FMR43 bit remains set to 1 (erase execution in progress) during erase-suspend operation. When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).
19.4.2.14 FMR44 Bit
When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress). The FMR44 bit remains set to 1 (program execution in progress) during program-suspend operation. When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).
19.4.2.15 FMR46 Bit
The FMR46 bit is set to 0 (reading disabled) during auto-program or auto-erase execution and set to 1 (reading enabled) in suspend mode. Do not access the flash memory while this bit is set to 0.
19.4.2.16 FMR47 Bit
Power consumption when reading the flash memory can be reduced by setting the FMR47 bit to 1 (enabled) in low-speed clock mode (XIN clock stops) and low-speed on-chip oscillator mode (XIN clock stops).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 405 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol FMR0 Bit Symbol FMR00 FMR01 FMR02
Address 01B7h
___
After Reset 00000001b Function 0 : Busy (w riting or erasing in progress) 1 : Ready 0 : CPU rew rite mode disabled 1 : CPU rew rite mode enabled 0 : Disables rew rite 1 : Enables rew rite 0 : Enables flash memory operation 1 : Stops flash memory (enters low -pow er consumption state and flash memory is reset) Set to 0. 0 : Completed successfully 1 : Terminated by error 0 : Completed successfully 1 : Terminated by error RW RO RW RW
Bit Name
RY/BY status flag CPU rew rite mode select bit(1) Block 0, 1 rew rite enable bit(2, 6) Flash memory stop bit(3, 5)
FMSTP
RW
-- (b5-b4) FMR06 FMR07
Reserved bits Program status flag(4) Erase status flag(4)
RW RO RO
NOTES: 1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. Enter read array mode and set this bit to 0. 2. Set this bit to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. 3. Set this bit by a program transferred to the RAM. 4. This bit is set to 0 by executing the clear status command. 5. This bit is enabled w hen the FMR01 bit is set to 1 (CPU rew rite mode enabled). When the FMR01 bit is set to 0, w riting 1 to the FMSTP bit causes the FMSTP bit to be set to 1. The flash memory does not enter low -pow er consumption state nor is it reset. 6. When setting the FMR01 bit to 0 (CPU rew rite mode disabled), the FMR02 bit is set to 0 (disables rew rite).
Figure 19.5
FMR0 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 406 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
1
000
Symbol Address 01B5h FMR1 Bit Symbol Bit Name -- Reserved bit (b0) FMR11 -- (b4-b2) FMR15 FMR16 -- (b7) EW1 mode select bit Reserved bits Block 0 rew rite disable bit
(2,3) (1, 2)
After Reset 1000000Xb Function When read, the content is undefined. 0 : EW0 mode 1 : EW1 mode Set to 0. 0 : Enables rew rite 1 : Disables rew rite 0 : Enables rew rite 1 : Disables rew rite Set to 1.
RW RO RW RW RW RW RW
Block 1 rew rite disable bit Reserved bit
(2,3)
NOTES: 1. To set this bit to 1, set it to 1 immediately after setting it first to 0 w hile the FMR01 bit is set to 1 (CPU rew rite mode enable). Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. 2. This bit is set to 0 by setting the FMR01 bit to 0 (CPU rew rite mode disabled). 3. When the FMR01 bit is set to 1 (CPU rew rite mode enabled), bits FMR15 and FMR16 can be w ritten to. To set this bit to 0, set it to 0 immediately after setting it first to 1. To set this bit to 1, set it to 1.
Figure 19.6
FMR1 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 407 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
Flash Memory Control Register 4
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol FMR4 Bit Symbol FMR40 FMR41 FMR42 FMR43 FMR44 -- (b5) FMR46 FMR47
Address 01B3h Bit Name Erase-suspend function enable bit(1) Erase-suspend request bit
(2)
After Reset 01000000b Function 0 : Disable 1 : Enable 0 : Erase restart 1 : Erase-suspend request
(3)
RW RW RW RW RO RO RO RO RW
Program-suspend request bit Erase command flag Program command flag Reserved bit Read status flag
0 : Program restart 1 : Program-suspend request 0 : Erase not executed 1 : Erase execution in progress 0 : Program not executed 1 : Program execution in progress Set to 0. 0 : Disables reading 1 : Enables reading
Low -pow er consumption read 0 : Disable mode enable bit (1, 4, 5) 1 : Enable
NOTES: 1. To set this bit to 1, set it to 1 immediately after setting it first to 0. Do not generate an interrupt betw een setting the bit to 0 and setting it to 1. 2. This bit is enabled w hen the FMR40 bit is set to 1 (enable) and it can be w ritten to during the period betw een issuing an erase command and completing the erase. (This bit is set to 0 during periods other than above.) In EW0 mode, it can be set to 0 or 1 by a program. In EW1 mode, it is automatically set to 1 if a maskable interrupt is generated during an erase operation w hile the FMR40 bit is set to 1. Do not set this bit to 1 by a program (0 can be w ritten). 3. The FMR42 bit is enabled only w hen the FMR40 bit is set to 1 (enable) and programming to the FMR42 bit is enabled until auto-programming ends after a program command is generated. (This bit is set to 0 during periods other than the above.) In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program. In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming w hen the FMR40 bit is set to 1. 1 cannot be w ritten to the FMR42 bit by a program. 4. In high-speed clock mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled). 5. Set the FMR01 bit in the FMR0 register to 0 (CPU rew rite mode disabled) in low -pow er consumption read mode.
Figure 19.7
FMR4 Register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 408 of 485
R8C/24 Group, R8C/25 Group Figure 19.8 shows the Timing of Suspend Operation.
19. Flash Memory
Erasure starts
Erasure suspends
Programming Programming Programming Programming Erasure starts suspends restarts ends restarts
Erasure ends
During erasure FMR00 bit in FMR0 register
1 0
During programming
During programming
During erasure
Remains 0 during suspend
FMR46 bit in FMR4 register
1 0
FMR44 bit in FMR4 register
1 0
FMR43 bit in FMR4 register
1 0
Remains 1 during suspend
Check that the FMR43 bit is set to 1 (during erase execution), and that the erase-operation has not ended.
Check that the FMR44 bit is set to 1 (during program execution), and that the program has not ended.
Check the status, and that the programming ends normally.
Check the status, and that the erasure ends normally.
The above figure shows an example of the use of program-suspend during programming following erase-suspend. NOTE: 1. If program-suspend is entered during erase-suspend, always restart programming.
Figure 19.8
Timing of Suspend Operation
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 409 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
Figure 19.9 shows the How to Set and Exit EW0 Mode. Figure 19.10 shows the How to Set and Exit EW1 Mode.
EW0 Mode Operating Procedure
Rewrite control program Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled)(2)
Set registers(1) CM0 and CM1 Execute software commands
Transfer a rewrite control program which uses CPU rewrite mode to the RAM.
Execute the read array command(3)
Jump to the rewrite control program which has been transferred to the RAM. (The subsequent process is executed by the rewrite control program in the RAM.)
Write 0 to the FMR01 bit (CPU rewrite mode disabled)
Jump to a specified address in the flash memory
NOTES: 1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. 2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1. Write to the FMR01 bit in the RAM. 3. Disable the CPU rewrite mode after executing the read array command.
Figure 19.9
How to Set and Exit EW0 Mode
EW1 Mode Operating Procedure
Program in ROM
Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled)(1) Write 0 to the FMR11 bit before writing 1 (EW1 mode)
Execute software commands
Write 0 to the FMR01 bit (CPU rewrite mode disabled)
NOTE: 1. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1.
Figure 19.10
How to Set and Exit EW1 Mode Page 410 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
19. Flash Memory
High-speed on-chip oscillator mode, low-speed on-chip oscillator mode (XIN clock stops), and low-speed clock mode (XIN clock stops) program Transfer a high-speed on-chip oscillator mode, lowspeed on-chip oscillator mode (XIN clock stops), and low-speed clock mode (XIN clock stops) program to the RAM. Write 0 to the FMR01 bit before writing 1 (CPU rewrite mode enabled)
Jump to the high-speed on-chip oscillator mode, lowspeed on-chip oscillator mode (XIN clock stops), and low-speed clock mode (XIN clock stops) program which has been transferred to the RAM. (The subsequent processing is executed by the program in the RAM.)
Write 1 to the FMSTP bit (flash memory stops. low power consumption mode)(1)
Switch the clock source for the CPU clock. Turn XIN off
Process in high-speed on-chip oscillator mode, low-speed on-chip oscillator mode (XIN clock stops), and low-speed clock mode (XIN clock stops) Turn XIN clock on wait until oscillation stabilizes switch the clock source for CPU clock(2)
Write 0 to the FMSTP bit (flash memory operation)
NOTES: 1. Set the FMR01 bit to 1 (CPU rewrite mode enabled) before setting the FMSTP bit to 1. 2. Before switching to a different clock source for the CPU, make sure the designated clock is stable. 3. Insert a 30 s wait time in a program. Do not access to the flash memory during this wait time.
Write 0 to the FMR01 bit (CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes (30 s)(3)
Jump to a specified address in the flash memory
Figure 19.11
Process to Reduce Power Consumption in High-Speed On-Chip Oscillator Mode, Low-Speed On-Chip Oscillator Mode (XIN Clock Stops) and Low-Speed Clock Mode (XIN Clock Stops)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 411 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.4.3
Software Commands
The software commands are described below. Read or write commands and data in 8-bit units. Table 19.4 Software Commands First Bus Cycle Command Read array Read status register Clear status register Program Block erase Mode Write Write Write Write Write Address x x x WA x Data Mode (D7 to D0) FFh 70h Read 50h 40h Write 20h Write Second Bus Cycle Address Data
(D7 to D0)
x WA BA
SRD WD D0h
SRD: Status register data (D7 to D0)
WA: Write address (ensure the address specified in the first bus cycle is the same address as the write address specified in the second bus cycle.) WD: Write data (8 bits) BA: Given block address x: Any specified address in the user ROM area
19.4.3.1
Read Array Command
The read array command reads the flash memory. The MCU enters read array mode when FFh is written in the first bus cycle. When the read address is entered in the following bus cycles, the content of the specified address can be read in 8-bit units. Since the MCU remains in read array mode until another command is written, the contents of multiple addresses can be read continuously. In addition, the MCU enters read array mode after a reset.
19.4.3.2
Read Status Register Command
The read status register command is used to read the status register. When 70h is written in the first bus cycle, the status register can be read in the second bus cycle (refer to 19.4.4 Status Registers). When reading the status register, specify an address in the user ROM area. Do not execute this command in EW1 mode. The MCU remains in read status register mode until the next read array command is written.
19.4.3.3
Clear Status Register Command
The clear status register command sets the status register to 0. When 50h is written in the first bus cycle, bits FMR06 to FMR07 in the FMR0 register and SR4 to SR5 in the status register are set to 0.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 412 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.4.3.4
Program Command
The program command writes data to the flash memory in 1-byte units. By writing 40h in the first bus cycle and data in the second bus cycle to the write address, an auto-program operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the same address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register can be used to determine whether auto-programming has completed. When suspend function disabled, the FMR00 bit is set to 0 during auto-programming and set to 1 when autoprogramming completes. When suspend function enabled, the FMR44 bit is set to 1 during auto-programming and set to 0 when auto-programming completes. The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been finished (refer to 19.4.5 Full Status Check). Do not write additions to the already programmed addresses. When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled), or the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), program commands targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), program commands targeting block 1 are not acknowledged. Figure 19.12 shows the Program Command (When Suspend Function Disabled). Figure 19.13 shows the Program Command (When Suspend Function Enabled). In EW1 mode, do not execute this command for any address which a rewrite control program is allocated. In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-programming starts and set back to 1 when auto-programming completes. In this case, the MCU remains in read status register mode until the next read array command is written. The status register can be read to determine the result of auto-programming after auto-programming has completed.
Start
Write the command code 40h to the write address
Write data to the write address
FMR00 = 1?
No
Yes
Full status check
Program completed
Figure 19.12
Program Command (When Suspend Function Disabled)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 413 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
EW0 Mode
Start
Maskable interrupt(1)
FMR40 = 1
FMR44 = 1 ? Yes FMR42 = 1(4)
No
Write the command code 40h to the write address
I = 1 (enable interrupt)(3) FMR46 = 1 ? Write data to the write address Yes Access flash memory FMR44 = 0 ? Yes Full status check REIT No FMR42 = 0 No Access flash memory
Program completed
EW1 Mode
Start
Maskable interrupt (2)
FMR40 = 1
Access flash memory
Write the command code 40h
REIT
I = 1 (enable interrupt)
Write data to the write address
FMR42 = 0
FMR44 = 0 ? Yes Full status check
No
Program completed
NOTES: 1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area. 2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend should be in interrupt enabled status. 3. When no interrupt is used, the instruction to enable interrupts is not needed. 4. td(SR-SUS) is needed until program is suspended after the FMR42 bit in the FMR4 register is set to 1.
Figure 19.13
Program Command (When Suspend Function Enabled) Page 414 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.4.3.5
Block Erase
When 20h is written in the first bus cycle and D0h is written to a given address of a block in the second bus cycle, an auto-erase operation (erase and verify) of the specified block starts. The FMR00 bit in the FMR0 register can be used to determine whether auto-erasure has completed. The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes. The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has completed (refer to 19.4.5 Full Status Check). When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled) or the FMR02 bit is set to 1 (rewriting enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), the block erase commands targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), block erase commands targeting block 1 are not acknowledged. Do not use the block erase command during program-suspend. Figure 19.14 shows the Block Erase Command (When Erase-Suspend Function Disabled). Figure 19.15 shows the Block Erase Command (When Erase-Suspend Function Enabled). In EW1 mode, do not execute this command for any address to which a rewrite control program is allocated. In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-erasure starts and set back to 1 when auto-erasure completes. In this case, the MCU remains in read status register mode until the next read array command is written.
Start
Write the command code 20h
Write D0h to a given block address
FMR00 = 1?
No
Yes
Full status check
Block erase completed
Figure 19.14
Block Erase Command (When Erase-Suspend Function Disabled)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 415 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
EW0 Mode
Start
Maskable interrupt(1)
FMR40 = 1
FMR43 = 1 ? Yes FMR41 = 1(4)
No
Write the command code 20h
I = 1 (enable interrupt)(3) FMR46 = 1 ? Write D0h to any block address Yes Access flash memory FMR00 = 1 ? Yes Full status check REIT Block erase completed No FMR41 = 0 No Access flash memory
EW1 Mode
Start
Maskable interrupt (2)
FMR40 = 1
Access flash memory
Write the command code 20h
REIT
I = 1 (enable interrupt)
Write D0h to any block address
FMR41 = 0
FMR00 = 1 ? Yes Full status check
No
Block erase completed
NOTES: 1. In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area. 2. td(SR-SUS) is needed until the interrupt request is acknowledged after it is generated. The interrupt to enter suspend should be in interrupt enabled status. 3. When no interrupt is used, the instruction to enable interrupts is not needed. 4. td(SR-SUS) is needed until erase is suspended after the FMR41 bit in the FMR4 register is set to 1.
Figure 19.15
Block Erase Command (When Erase-Suspend Function Enabled) Page 416 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.4.4
Status Registers
The status register indicates the operating status of the flash memory and whether an erase or program operation has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and FMR07 in the FMR0 register. Table 19.5 lists the Status Register Bits. In EW0 mode, the status register can be read in the following cases: * When a given address in the user ROM area is read after writing the read status register command * When a given address in the user ROM area is read after executing program or block erase command but before executing the read array command.
19.4.4.1
Sequencer Status (Bits SR7 and FMR00)
The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy) during autoprogramming and auto-erasure, and is set to 1 (ready) at the same time the operation completes.
19.4.4.2
Erase Status (Bits SR5 and FMR07)
Refer to 19.4.5 Full Status Check.
19.4.4.3
Program Status (Bits SR4 and FMR06)
Refer to 19.4.5 Full Status Check. Table 19.5 Status Register Bits FMR0 Register Bit - - - - FMR06 FMR07 - FMR00 Status Name Reserved Reserved Reserved Reserved Program status Erase status Reserved Sequencer status Description 0 - - - - Completed normally Completed normally - Busy - - - - Error Error - Ready 1 - - - - 0 0 - 1 Value after Reset
Status Register Bit SR0 (D0) SR1 (D1) SR2 (D2) SR3 (D3) SR4 (D4) SR5 (D5) SR6 (D6) SR7 (D7)
D0 to D7: Indicate the data bus which is read when the read status register command is executed. Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command. When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the program and block erase commands cannot be accepted.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 417 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.4.5
Full Status Check
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an error. Therefore, checking these status bits (full status check) can be used to determine the execution result. Table 19.6 lists the Errors and FMR0 Register Status. Figure 19.16 shows the Full Status Check and Handling Procedure for Individual Errors. Table 19.6 Errors and FMR0 Register Status Error Occurrence Condition * When a command is not written correctly * When invalid data other than that which can be written in the second bus cycle of the block erase command is written (i.e., other than D0h or FFh)(1) * When the program command or block erase command is executed while rewriting is disabled by the FMR02 bit in the FMR0 register, or the FMR15 or FMR16 bit in the FMR1 register. * When an address not allocated in flash memory is input during erase command input * When attempting to erase the block for which rewriting is disabled during erase command input. * When an address not allocated in flash memory is input during write command input. * When attempting to write to a block for which rewriting is disabled during write command input. * When the block erase command is executed but autoerasure does not complete correctly * When the program command is executed but not autoprogramming does not complete.
FMR0 Register (Status Register) Status Error FMR07(SR5) FMR06(SR4) 1 1 Command sequence error
1 0
0 1
Erase error Program error
NOTE: 1. The MCU enters read array mode when FFh is written in the second bus cycle of these commands. At the same time, the command code written in the first bus cycle is disabled.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 418 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
Command sequence error
Full status check Execute the clear status register command (set these status flags to 0) FMR06 = 1 and FMR07 = 1? No Re-execute the command Yes
Command sequence error Check if command is properly input
FMR07 = 1? No
Yes
Erase error
Erase error
Execute the clear status register command (set these status flags to 0)
Erase command re-execution times 3 times? Yes Yes Re-execute block erase command
No
Block targeting for erasure cannot be used
FMR06 = 1? No
Program error
Program error
Execute the clear status register command (set these status flags to 0) Full status check completed Specify the other address besides the write address where the error occurs for the program address(1) NOTE: 1. To rewrite to the address where the program error occurs, check if the full status check is complete normally and write to the address after the block erase command is executed.
Re-execute program command
Figure 19.16
Full Status Check and Handling Procedure for Individual Errors
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 419 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.5
Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a serial programmer which is suitable for the MCU. There are three types of Standard serial I/O modes: * Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer * Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer * Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial programmer This MCU uses Standard serial I/O mode 2 and Standard serial I/O mode 3. Refer to Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator. Contact the manufacturer of your serial programmer for details. Refer to the user's manual of your serial programmer for instructions on how to use it. Table 19.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 19.8 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 3), and Figure 19.17 shows Pin Connections for Standard Serial I/O Mode 3. After processing the pins shown in Table 19.8 and rewriting the flash memory using the programmer, apply "H" to the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.
19.5.1
ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer and those written in the flash memory match (refer to 19.3 Functions to Prevent Rewriting of Flash Memory). Table 19.7 Pin VCC,VSS RESET P4_6/XIN P4_7/XOUT P4_3/XCIN P4_4/XCOUT P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0, P3_1, P3_3 to P3_5, P3_7 P4_2/VREF, P4_5 P6_0 to P6_5 MODE P6_6 P6_7 Pin Functions (Flash Memory Standard Serial I/O Mode 2) Name Power input Reset input P4_6 input/clock input I/O Description Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin. Reset input pin. Connect a ceramic resonator or crystal oscillator between the XIN and XOUT pins.
I I
P4_7 input/clock output I/O P4_3 input/clock input I Connect crystal oscillator between pins XCIN and XCOUT.
P4_4 input/clock output I/O Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P6 MODE TXD output RXD input I I I I I I I O I Input "H" or "L" level signal or leave the pin open. Input "H" or "L" level signal or leave the pin open. Input "H" or "L" level signal or leave the pin open. Input "H" or "L" level signal or leave the pin open. Input "H" or "L" level signal or leave the pin open. Input "H" or "L" level signal or leave the pin open. Input "L" level signal. Serial data output pin. Serial data input pin.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 420 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
Table 19.8 Pin VCC,VSS RESET P4_6/XIN P4_7/XOUT P4_3/XCIN P4_4/XCOUT
Pin Functions (Flash Memory Standard Serial I/O Mode 3) Name Power input Reset input P4_6 input/clock input P4_7 input/clock output P4_3 input/clock input P4_4 input/clock output Input port P0 Input port P1 Input port P2 Input port P3 I/O Description Apply the voltage guaranteed for programming and erasure to the VCC pin and 0 V to the VSS pin. Reset input pin.
I I
Connect a ceramic resonator or crystal oscillator between the XIN and XOUT pins when connecting I/O external oscillator. Apply "H" and "L" or leave the pin open when using as input port. Connect crystal oscillator between pins XCIN and XCOUT when connecting external oscillator. Apply "H" I/O and "L" or leave the pin open when using as a port. I I I I Input "H" or "L" level signal or leave the pin open. Input "H" or "L" level signal or leave the pin open. Input "H" or "L" level signal or leave the pin open. Input "H" or "L" level signal or leave the pin open.
I
P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0, P3_1, P3_3 to P3_5, P3_7 P4_2/VREF, P4_5 P6_0 to P6_7 MODE
Input port P4 Input port P6 MODE
I
Input "H" or "L" level signal or leave the pin open.
I Input "H" or "L" level signal or leave the pin open. I/O Serial data I/O pin. Connect to the flash programmer.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 421 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
39
38
37
36
35
34
33
32
31
30
29
28
40 41 42 43 44 45 46 47 48 49 50 51 52
10 11 12 13 1 2 3 4 5 6 7 8 9
27
26 25 24 23 22
R8C/24 Group R8C/25 Group
21 20 19 18 17 16 15 14
MODE
VSS VCC
Connect oscillator circuit(1) Mode setting Signal MODE RESET Value
Voltage from programmer
Package: PLQP0052JA-A
NOTE: 1. It is not necessary to connect an oscillating circuit when operating with the on-chip oscillator clock.
VSS VCC
Figure 19.17
Pin Connections for Standard Serial I/O Mode 3
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 422 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.5.1.1
Example of Circuit Application in Standard Serial I/O Mode
Figure 19.18 shows an Example of Pin Processing in Standard Serial I/O Mode 2, and Figure 19.19 shows an Example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the programmer, refer to the manual of your serial programmer for details.
MCU
Data Output
TXD
Data Input
RXD MODE
NOTES: 1. In this example, modes are switched between single-chip mode and standard serial I/O mode by controlling the MODE input with a switch. 2. Connecting the oscillation is necessary. Set the main clock frequency 1 MHz to 20 MHz. Refer to Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806).
Figure 19.18
Example of Pin Processing in Standard Serial I/O Mode 2
MCU
MODE I/O MODE
Reset input
RESET
User reset signal
NOTES: 1. Controlled pins and external circuits vary depending on the programmer. Refer to the programmer manual for details. 2. In this example, modes are switched between single-chip mode and standard serial I/O mode by connecting a programmer. 3. When operating with the on-chip oscillator clock, it is not necessary to connect an oscillating circuit.
Figure 19.19
Example of Pin Processing in Standard Serial I/O Mode 3 Page 423 of 485
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.6
Parallel I/O Mode
Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read, program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the manufacturer of the parallel programmer for more information, and refer to the user's manual of the parallel programmer for details on how to use it. ROM areas shown in Figures 19.1 and 19.2 can be rewritten in parallel I/O mode.
19.6.1
ROM Code Protect Function
The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to 19.3 Functions to Prevent Rewriting of Flash Memory.)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 424 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.7 19.7.1
Notes on Flash Memory CPU Rewrite Mode Operating Speed
19.7.1.1
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
19.7.1.2
Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK.
19.7.1.3
Interrupts
Table 19.9 lists the EW0 Mode Interrupts, and Table 19.10 lists the EW1 Mode Interrupts. Table 19.9 EW0 Mode Interrupts When Maskable Interrupt Request is Acknowledged Any interrupt can be used by allocating a vector in RAM When Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Request is Acknowledged Once an interrupt request is acknowledged, auto-programming or auto-erasure is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts after the fixed period and the flash memory restarts. Since the block during autoerasure or the address during autoprogramming is forcibly stopped, the normal value may not be read. Execute auto-erasure again and ensure it completes normally. Since the watchdog timer does not stop during the command operation, interrupt requests may be generated. Reset the watchdog timer regularly.
Mode
Status
EW0 During auto-erasure
Auto-programming
NOTES: 1. Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM. 2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 425 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
Table 19.10
EW1 Mode Interrupts When Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Request is Acknowledged Auto-erasure is suspended after Once an interrupt request is acknowledged, auto-programming or td(SR-SUS) and interrupt auto-erasure is forcibly stopped handling is executed. Autoimmediately and the flash memory is erasure can be restarted by reset. Interrupt handling starts after the setting the FMR41 bit in the FMR4 register to 0 (erase restart) fixed period and the flash memory restarts. Since the block during autoafter interrupt handling erasure or the address during autocompletes. Auto-erasure has priority and the programming is forcibly stopped, the normal value may not be read. Execute interrupt request auto-erasure again and ensure it acknowledgement is put on completes normally. standby. Interrupt handling is Since the watchdog timer does not stop executed after auto-erasure during the command operation, completes. Auto-programming is suspended interrupt requests may be generated. Reset the watchdog timer regularly after td(SR-SUS) and interrupt using the erase-suspend function. handling is executed. Auto-programming can be restarted by setting the FMR42 bit in the FMR4 register to 0 (program restart) after interrupt handling completes. Auto-programming has priority and the interrupt request acknowledgement is put on standby. Interrupt handling is executed after auto-programming completes. When Maskable Interrupt Request is Acknowledged
Mode
Status
EW1 During auto-erasure (erase-suspend function enabled)
During auto-erasure (erase-suspend function disabled)
During autoprogramming (program suspend function enabled)
During autoprogramming (program suspend function disabled)
NOTES: 1. Do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in ROM. 2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 426 of 485
R8C/24 Group, R8C/25 Group
19. Flash Memory
19.7.1.4
How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt between writing 0 and 1.
19.7.1.5
Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode.
19.7.1.6
Program
Do not write additions to the already programmed address.
19.7.1.7
Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
19.7.1.8
Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 427 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
20. Electrical Characteristics
The electrical characteristics of N version (Topr = -20 to 85C) and D version (Topr = -40 to 85C) are listed below. Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr = -20 to 105C). Table 20.1
Symbol VCC/AVCC VI VO Pd Topr Tstg
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature Condition Rated Value -0.3 to 6.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 500(1) -20 to 85 (N version) / -40 to 85 (D version) -65 to 150 Unit V V V mW
C C
Topr = 25C
NOTE: 1. 300 mW for the PTLG0064JA-A package.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 428 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.2
Symbol VCC/AVCC VSS/AVSS VIH VIL IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XIN)
Recommended Operating Conditions
Parameter Supply voltage Supply voltage Input "H" voltage Input "L" voltage Peak sum output "H" current Average sum output "H" current Peak output "H" current Average output "H" current Peak sum output "L" current Average sum output "L" current Peak output "L" current Conditions Min. 2.2 - 0.8 VCC 0 -
- - - - - - - - - - -
Sum of all pins IOH(peak) Sum of all pins IOH(avg) Except P2_0 to P2_7 P2_0 to P2_7 Except P2_0 to P2_7 P2_0 to P2_7 Sum of all pins IOL(peak) Sum of all pins IOL(avg)
Standard Typ. - 0 - - -
- - - - - - - - - - - - - - - - - - 125
Max. 5.5 - VCC 0.2 VCC -160 -80 -10 -40 -5 -20 160 80 10 40 5 20 20 10 5 70 20 10 5 -
Unit V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz MHz MHz MHz kHz
Except P2_0 to P2_7 P2_0 to P2_7 Average output Except P2_0 to P2_7 "L" current P2_0 to P2_7 XIN clock input oscillation frequency
f(XCIN) -
XCIN clock input oscillation frequency System clock OCD2 = 0 XlN clock selected OCD2 = 1 On-chip oscillator clock selected
3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V 2.2 V VCC 5.5 V 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V FRA01 = 0 Low-speed on-chip oscillator clock selected FRA01 = 1 High-speed on-chip oscillator clock selected 3.0 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.7 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.2 V VCC 5.5 V
0 0 0 0 0 0 0 -
-
-
20
MHz
-
-
10
MHz
-
-
5
MHz
NOTES: 1. VCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 429 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.3
Symbol
- -
A/D Converter Characteristics
Parameter Resolution Absolute accuracy Conditions Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 3.3 V AD = 10 MHz, Vref = AVCC = 3.3 V AD = 5 MHz, Vref = AVCC = 2.2 V AD = 5 MHz, Vref = AVCC = 2.2 V Vref = AVCC AD = 10 MHz, Vref = AVCC = 5.0 V AD = 10 MHz, Vref = AVCC = 5.0 V Min. - - - - - - - 10 3.3 2.8 2.2 0 0.25 1 0.25 1 Standard Typ. Max. - 10 - 3 - 2 - 5 - 2 - 5 - 2 - 40 - - - - - AVCC - AVCC
- - - -
Unit Bit LSB LSB LSB LSB LSB LSB k s s V V MHz MHz MHz MHz
10-bit mode 8-bit mode 10-bit mode 8-bit mode 10-bit mode 8-bit mode
Rladder tconv Vref VIA
-
Resistor ladder Conversion time 10-bit mode 8-bit mode Reference voltage Analog input voltage(2) A/D operating Without sample and hold clock frequency With sample and hold Without sample and hold With sample and hold
Vref = AVCC = 2.7 to 5.5 V Vref = AVCC = 2.7 to 5.5 V Vref = AVCC = 2.2 to 5.5 V Vref = AVCC = 2.2 to 5.5 V
10 10 5 5
NOTES: 1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode.
P0 P1 P2 P3 P4 P6
30pF
Figure 20.1
Ports P0 to P4, P6 Timing Measurement Circuit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 430 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.4
Symbol
- - -
Flash Memory (Program ROM) Electrical Characteristics
Parameter Program/erase endurance(2) Byte program time Block erase time Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(7) Ambient temperature = 55C Conditions R8C/24 Group R8C/25 Group Min. 100(3) 1,000(3) - - - 650 0
-
Standard Typ. -
-
Max. -
-
Unit times times
s
td(SR-SUS)
- - - - - - -
50 0.4 -
- - - - - - -
400 9 97+CPU clock x 6 cycles -
-
s
s s
ns
s
2.7 2.2 0 20
3+CPU clock x 4 cycles 5.5 5.5 60 -
V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 431 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.5
Symbol
- - - - -
Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Parameter Program/erase endurance(2) Byte program time (program/erase endurance 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance 1,000 times) Block erase time (program/erase endurance > 1,000 times) Time delay from suspend request until suspend Interval from erase start/restart until following suspend request Interval from program start/restart until following suspend request Time from suspend until program/erase restart Program, erase voltage Read voltage Program, erase temperature Data hold time(9) Ambient temperature = 55 C Conditions Min. 10,000(3) -
- - - -
Standard Typ. - 50 65 0.2 0.3
- - - - - - - -
Max. - 400
-
Unit times
s s
9
-
s s
s s
td(SR-SUS)
- - - - - - -
650 0
-
97+CPU clock x 6 cycles -
-
ns
s
2.7 2.2 -20(8) 20
3+CPU clock x 4 cycles 5.5 5.5 85
-
V V C year
NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. -40C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 432 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Suspend request (maskable interrupt request)
FMR46
Fixed time Clock-dependent time Access restart
td(SR-SUS)
Figure 20.2
Time delay until Suspend
Table 20.6
Symbol Vdet0
-
Voltage Detection 0 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(2) MCU operating voltage minimum value Condition Min. 2.2 - - 2.2 Standard Typ. Max. 2.3 2.4 0.9 - - 300
- -
Unit V
A s
VCA25 = 1, VCC = 5.0 V
td(E-A) Vccmin
V
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0.
Table 20.7
Symbol Vdet1
- -
Voltage Detection 1 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage monitor 1 interrupt request generation Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) time(2) VCA26 = 1, VCC = 5.0 V Condition Min. 2.70 -
- -
Standard Typ. Max. 2.85 3.00 40 - 0.6 -
- 100
Unit V
s A s
td(E-A)
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0.
Table 20.8
Symbol Vdet2
- -
Voltage Detection 2 Circuit Electrical Characteristics
Parameter Voltage detection level Voltage monitor 2 interrupt request generation time(2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts(3) VCA27 = 1, VCC = 5.0 V Condition Min. 3.3
- - -
Standard Typ. Max. 3.6 3.9 40 0.6 -
- - 100
Unit V
s A s
td(E-A)
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 433 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.9
Symbol Vpor1 Vpor2 trth
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Parameter Power-on reset valid voltage(4) Power-on reset or voltage monitor 0 reset valid voltage External power VCC rise gradient(2) Condition Min. - 0 20 Standard Typ. -
- -
Unit Max. 0.1 Vdet0
-
V V mV/msec
NOTES: 1. The measurement condition is Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC 1.0 V. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20C Topr 85C, maintain tw(por1) for 3,000 s or more if -40C Topr < -20C.
Vdet0(3) 2.2 V External Power VCC Vpor1 tw(por1) Sampling time(1, 2) trth Vpor2 trth
Vdet0(3)
Internal reset signal ("L" valid) 1 x 32 fOCO-S 1 x 32 fOCO-S
NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details.
Figure 20.3
Power-on Reset Circuit Electrical Characteristics
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 434 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.10
Symbol fOCO40M
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter High-speed on-chip oscillator frequency temperature * supply voltage dependence Condition VCC = 4.75 to 5.25 V 0C Topr 60C(2) VCC = 4.5 to 5.5 V -20C Topr 85C VCC = 4.5 to 5.5 V -40C Topr 85C VCC = 3.0 to 5.5 V -20C Topr 85C(2) VCC = 3.0 to 5.5 V -40C Topr 85C(2) VCC = 2.7 to 5.5 V -20C Topr 85C(2) VCC = 2.7 to 5.5 V -40C Topr 85C(2) VCC = 2.2 to 5.5 V -20C Topr 85C(3) VCC = 2.2 to 5.5 V -40C Topr 85C(3) VCC = 5.0 V, Topr = 25C VCC = 3.0 to 5.5 V -20C Topr 85C Adjust FRA1 register (value after reset) to -1 VCC = 5.0 V, Topr = 25C Min. 39.2 38.8 38.4 38.8 38.4 38 37.6 35.2 34
- -3%
Standard Typ. 40 40 40 40 40 40 40 40 40 36.864 -
- +0.3
Max. 40.8 40.8 40.8 41.2 41.6 42 42.4 44.8 46
Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz %
- MHz s A
High-speed on-chip oscillator frequency when correction value in FRA7 register is written to FRA1 register(4)
- - - -
3% F7h - 100 -
Value in FRA1 register after reset Oscillation frequency adjustment unit of highspeed on-chip oscillator Oscillation stability time Self power consumption at oscillation
08h -
- -
10 400
NOTES: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. Standard values when the FRA1 register value after reset is assumed. 3. Standard values when the corrected value of the FRA6 register has been written to the FRA1 register. 4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode.
Table 20.11
Symbol fOCO-S
- -
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation Condition Min. 30 - - Standard Typ. 125 10 15 Max. 250 100 - Unit kHz s A
VCC = 5.0 V, Topr = 25C
NOTE: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.
Table 20.12
Symbol td(P-R) td(R-S)
Power Supply Circuit Timing Characteristics
Parameter Condition Min. 1
-
Time for internal power supply stabilization during power-on(2) STOP exit time(3)
Standard Typ. Max. - 2000
-
Unit
s s
150
NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 435 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.13
Symbol tSUCYC tHI tLO tRISE tFALL tSU tH tLEAD tLAG tOD tSA tOR
Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Parameter SSCK clock cycle time SSCK clock "H" width SSCK clock "L" width SSCK clock rising time SSCK clock falling time Conditions Min. 4 0.4 0.4 -
- - - 100 1
Standard Typ. -
- - - - - - - - - - - - - - -
Unit Max. - 0.6 0.6 1 1 1 1
- - - -
tCYC(2) tSUCYC tSUCYC tCYC(2) s tCYC(2) s ns tCYC(2) ns ns tCYC(2) ns ns ns ns
Master Slave Master
Slave SSO, SSI data input setup time SSO, SSI data input hold time SCS setup time Slave Slave
1tCYC + 50 1tCYC + 50
-
SCS hold time SSO, SSI data output delay time SSI slave access time SSI slave out open time 2.7 V VCC 5.5 V 2.2 V VCC < 2.7 V 2.7 V VCC 5.5 V 2.2 V VCC < 2.7 V
1 1.5tCYC + 100 1.5tCYC + 200 1.5tCYC + 100 1.5tCYC + 200
- - - -
NOTES: 1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 436 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH tHI tFALL tRISE
SSCK (output) (CPOS = 1)
tLO tHI
SSCK (output) (CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
CPHS, CPOS: Bits in SSMR register
Figure 20.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 437 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0 SCS (input)
VIH or VOH VIH or VOH tLEAD tHI tFALL tRISE tLAG
SSCK (input) (CPOS = 1)
tLO tHI
SSCK (input) (CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
CPHS, CPOS: Bits in SSMR register
Figure 20.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 438 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
tHI VIH or VOH
SSCK
VIH or VOH tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 20.6
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 439 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.14
Symbol tSCL tSCLH tSCLL tsf tSP tBUF tSTAH tSTAS tSTOP tSDAS tSDAH
Timing Requirements of I2C bus Interface(1)
Parameter Condition Standard Typ. - 12tCYC + 600(2) - 3tCYC + 300(2) Min. 5tCYC + - - 500(2)
- - - - - - - - -
Unit Max. -
- -
SCL input cycle time SCL input "H" width SCL input "L" width SCL, SDA input fall time SCL, SDA input spike pulse rejection time SDA input bus-free time Start condition input hold time Retransmit start condition input setup time Stop condition input setup time Data input setup time Data input hold time
ns ns ns ns ns ns ns ns ns ns ns
300 1tCYC(2) -
- - - - -
5tCYC(2) 3tCYC(2) 3tCYC(2) 3tCYC(2) 1tCYC + 20(2) 0
NOTES: 1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. 1tCYC = 1/f1(s)
VIH
SDA
VIL tBUF tSTAH tSCLH tSTAS tSP tSTOP
SCL
P(2) S(1) tsf tSCLL tSCL Sr(3) tsr tSDAH tSDAS P(2)
NOTES: 1. Start condition 2. Stop condition 3. Retransmit start condition
Figure 20.7
I/O Timing of I2C bus Interface
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 440 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.15
Symbol VOH
Electrical Characteristics (1) [VCC = 5 V]
Parameter Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 A Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW Standard Min. Typ. VCC - 2.0 - VCC - 0.5 - VCC - 2.0 - VCC - 2.0 - VCC - 2.0 - VCC - 2.0 - - - - - - - - - - - - - 0.1 0.5 Max. VCC VCC VCC VCC VCC VCC 2.0 0.45 2.0 2.0 2.0 2.0 - Unit V V V V V V V V V V V V V
Output "H" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7 XOUT
IOH = -20 mA IOH = -5 mA IOH = -1 mA IOH = -500 A
VOL
Output "L" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7 XOUT
IOL = 20 mA IOL = 5 mA IOL = 1 mA IOL = 500 A
VT+-VT-
Hysteresis
INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 5 V, Vcc = 5V VI = 0 V, Vcc = 5V VI = 0 V, Vcc = 5V XIN XCIN During stop mode
0.1
- -
1.0
- -
-
V
A A k M
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage
30 -
-
50 1.0 18
-
5.0 -5.0 167 -
- -
M V
1.8
NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 441 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.16
Electrical Characteristics (2) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Condition XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 Min. - Standard Typ. Max. 10 17 Unit mA
Symbol ICC
Parameter Power supply High-speed current clock mode (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS
-
9
15
mA
-
6
-
mA
-
5
-
mA
-
4
-
mA
-
2.5
-
mA
High-speed on-chip oscillator mode
-
10
15
mA
-
4
-
mA
-
5.5
10
mA
-
2.5
-
mA
Low-speed on-chip oscillator mode Low-speed clock mode
-
130
300
A
-
130
300
A
-
30
-
A
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 442 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.17
Electrical Characteristics (3) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Condition XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 Increase during Without sample & hold A/D converter With sample & hold operation Stop mode XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 25 75 Unit
A
Symbol ICC
Parameter Power supply Wait mode current (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS
-
23
60
A
-
4.0
-
A
-
2.2
-
A
- - -
2.6 1.6 0.8
- -
mA mA
A
3.0
-
1.2
-
A
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 443 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) [VCC = 5 V] Table 20.18
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
XIN Input, XCIN Input
Parameter Standard Min. Max. 50 - 25 - 25 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 5 V
XIN input
tWL(XIN) tC(XCIN) tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 20.8
XIN Input and XCIN Input Timing Diagram when VCC = 5 V
Table 20.19
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 100 - 40 - 40 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 5 V
TRAIO input
tWL(TRAIO)
Figure 20.9
TRAIO Input Timing Diagram when VCC = 5 V
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 444 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.20
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 5 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 20.10
Serial Interface Timing Diagram when VCC = 5 V
Table 20.21
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input
Parameter INT0 input "H" width INT0 input "L" width Standard Min. Max. - 250(1) 250(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 20.11
External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 445 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.22
Symbol VOH
Electrical Characteristics (3) [VCC = 3 V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOH = -5 mA IOH = -1 mA IOH = -0.1 mA IOH = -50 A Min. VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5
-
Output "H" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
Standard Typ. -
- - - - - - - - -
Max. VCC VCC VCC VCC VCC 0.5 0.5 0.5 0.5 0.5
-
Unit V V V V V V V V V V V
XOUT
VOL
Output "L" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
IOL = 5 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 A
- - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 3 V, Vcc = 3V VI = 0 V, Vcc = 3V VI = 0 V, Vcc = 3V XIN XCIN During stop mode
0.1
0.3
0.1
- -
0.4
- -
-
V
A A k M M V
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage
66 - - 1.8
160 3.0 18 -
4.0 -4.0 500 - - -
NOTE: 1. VCC =2.7 to 3.3 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 446 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.23
Electrical Characteristics (4) [Vcc = 3 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 Without sample & hold With sample & hold XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 6 - Unit mA
Symbol ICC
Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS
-
2
-
mA
High-speed onchip oscillator mode
-
5
9
mA
-
2
-
mA
Low-speed onchip oscillator mode Low-speed clock mode
-
130
300
A
-
130
300
A
-
30
-
A
Wait mode
-
25
70
A
-
23
55
A
-
3.8
-
A
-
2.0
-
A
Increase during A/D converter operation Stop mode
- - -
0.9 0.5 0.7
- -
mA mA
A
3.0
-
1.1
-
A
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 447 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25C) [VCC = 3 V] Table 20.24
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
XIN Input, XCIN Input
Parameter Standard Min. Max. 100 - 40 - 40 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 3 V
XIN input
tWL(XIN) tC(XCIN) tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 20.12
XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Table 20.25
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 300 - 120 - 120 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 3 V
TRAIO input
tWL(TRAIO)
Figure 20.13
TRAIO Input Timing Diagram when VCC = 3 V
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 448 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.26
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi Input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 3 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 20.14
Serial Interface Timing Diagram when VCC = 3 V
Table 20.27
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input
Parameter INT0 input "H" width INT0 input "L" width Standard Min. Max. - 380(1) 380(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 20.15
External Interrupt INTi Input Timing Diagram when VCC = 3 V
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 449 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.28
Symbol VOH
Electrical Characteristics (5) [VCC = 2.2 V]
Parameter Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW IOH = -2 mA IOH = -1 mA IOH = -0.1 mA IOH = -50 A Min. VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5 VCC - 0.5
-
Output "H" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
Standard Typ. -
- - - - - - - - -
Max. VCC VCC VCC VCC VCC 0.5 0.5 0.5 0.5 0.5
-
Unit V V V V V V V V V V V
XOUT
VOL
Output "L" voltage
Except P2_0 to P2_7, XOUT P2_0 to P2_7
IOL = 2 mA IOL = 1 mA IOL = 0.1 mA IOL = 50 A
- - - -
XOUT
VT+-VT-
Hysteresis
INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, CLK1, SSI, SCL, SDA, SSO RESET VI = 2.2 V VI = 0 V VI = 0 V XIN XCIN During stop mode
0.05
0.3
0.05
- -
0.15
- -
-
V
A A k M M V
IIH IIL RPULLUP RfXIN RfXCIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance Feedback resistance RAM hold voltage
100 - - 1.8
200 5 35 -
4.0 -4.0 600 - - -
NOTE: 1. VCC = 2.2 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 5 MHz, unless otherwise specified.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 450 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.29
Electrical Characteristics (6) [Vcc = 2.2 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.)
Parameter Condition XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz FMR47 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz Program operation on RAM Flash memory off, FMSTP = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (high drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off XCIN clock oscillator on = 32 kHz (low drive) While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 Without sample & hold With sample & hold XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 Min. - Standard Typ. Max. 3.5 - Unit mA
Symbol ICC
Power supply current High-speed clock (VCC = 2.2 to 2.7 V) mode Single-chip mode, output pins are open, other pins are VSS
-
1.5
-
mA
High-speed onchip oscillator mode
-
3.5
-
mA
-
1.5
-
mA
Low-speed onchip oscillator mode Low-speed clock mode
-
100
230
A
-
100
230
A
-
25
-
A
Wait mode
-
22
60
A
-
20
55
A
-
3.0
-
A
-
1.8
-
A
Increase during A/D converter operation Stop mode
- - -
0.4 0.3 0.7
- -
mA mA
A
3.0
-
1.1
-
A
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 451 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25C) [VCC = 2.2 V] Table 20.30
Symbol tc(XIN) tWH(XIN) tWL(XIN) tc(XCIN) tWH(XCIN) tWL(XCIN) XIN input cycle time XIN input "H" width XIN input "L" width XCIN input cycle time XCIN input "H" width XCIN input "L" width
XIN Input, XCIN Input
Parameter Standard Min. Max. 200 - 90 - 90 - 14 - 7 - 7 - Unit ns ns ns s s s
tC(XIN) tWH(XIN)
VCC = 2.2 V
XIN input
tWL(XIN) tC(XCIN) tWH(XCIN)
XCIN input
tWL(XCIN)
Figure 20.16
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Table 20.31
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. Max. 500 - 200 - 200 - Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
VCC = 2.2 V
TRAIO input
tWL(TRAIO)
Figure 20.17
TRAIO Input Timing Diagram when VCC = 2.2 V
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 452 of 485
R8C/24 Group, R8C/25 Group
20. Electrical Characteristics
Table 20.32
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 or 1
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. Max. 800 - 400 - 400 - - 200 0 - 150 - 90 - Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
VCC = 2.2 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0 or 1
Figure 20.18
Serial Interface Timing Diagram when VCC = 2.2 V
Table 20.33
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input
Parameter INT0 input "H" width INT0 input "L" width Standard Min. Max. (1) - 1000 1000(2)
-
Unit ns ns
NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0 to 3
Figure 20.19
External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 453 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21. Usage Notes
21.1 21.1.1 Notes on Clock Generation Circuit Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction which sets the CM10 bit to 1 (stop mode) and the program stops. Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets the CM10 bit to 1. * Program example to enter stop mode BCLR BSET FSET BSET JMP.B LABEL_001 : NOP NOP NOP NOP
1,FMR0 0,PRCR I 0,CM1 LABEL_001
; CPU rewrite mode disabled ; Protect disabled ; Enable interrupt ; Stop mode
21.1.2
Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and execute the WAIT instruction. An instruction queue pre-reads 4 bytes from the WAIT instruction and the program stops. Insert at least 4 NOP instructions after the WAIT instruction. * Program example to execute the WAIT instruction BCLR 1,FMR0 FSET I WAIT NOP NOP NOP NOP
; CPU rewrite mode disabled ; Enable interrupt ; Wait mode
21.1.3
Oscillation Stop Detection Function
Since the oscillation stop detection function cannot be used if the XIN clock frequency is 2 MHz or below, set bits OCD1 to OCD0 to 00b.
21.1.4
Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system. To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the feedback resistor to the chip externally.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 454 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.2 21.2.1
Notes on Interrupts Reading Address 00000h
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0. If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be generated.
21.2.2
SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an interrupt is acknowledged before setting a value in the SP, the program may run out of control.
21.2.3
External Interrupt and Key Input Interrupt
Either "L" level or an "H" level of width shown in the Electrical Characteristics is necessary for the signal input to pins INT0 to INT3 and pins KI0 to KI3, regardless of the CPU clock. For details, refer to Table 20.21 (VCC = 5V), Table 20.27 (VCC = 3V), Table 20.33 (VCC = 2.2V) External Interrupt INTi (i = 0 to 3) Input.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 455 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.2.4
Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source. In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripheral function involves interrupt sources, edge polarities, and timing, set the IR bit to 0 (no interrupt requested) after the change. Refer to the individual peripheral function for its related interrupts. Figure 21.1 shows an Example of Procedure for Changing Interrupt Sources.
Interrupt source change
Disable interrupts(2, 3)
Change interrupt source (including mode of peripheral function)
Set the IR bit to 0 (interrupt not requested) using the MOV instruction(3)
Enable interrupts (2, 3)
Change completed
IR bit:
The interrupt control register bit of an interrupt whose source is changed.
NOTES: 1. Execute the above settings individually. Do not execute two or more settings at once (by one instruction). 2. To prevent interrupt requests from being generated, disable the peripheral function before changing the interrupt source. In this case, use the I flag if all maskable interrupts can be disabled. If all maskable interrupts cannot be disabled, use bits ILVL0 to ILVL2 of the interrupt whose source is changed. 3. Refer to 12.6.5 Changing Interrupt Control Register Contents for the instructions to be used and usage notes.
Figure 21.1
Example of Procedure for Changing Interrupt Sources
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 456 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.2.5
Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests corresponding to that register are generated. If interrupt requests may be generated, disable interrupts before changing the interrupt control register contents. (b) When changing the contents of an interrupt control register after disabling interrupts, be careful to choose appropriate instructions. Changing any bit other than IR bit If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored. If this causes a problem, use the following instructions to change the register: AND, OR, BCLR, BSET Changing IR bit If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used. Therefore, use the MOV instruction to set the IR bit to 0. (c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs below. Refer to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer. Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register is changed INT_SWITCH1: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h NOP ; NOP FSET I ; Enable interrupts
Example 2: Use dummy read to delay FSET instruction INT_SWITCH2: FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h MOV.W MEM,R0 ; Dummy read FSET I ; Enable interrupts Example 3: Use POPC instruction to change I flag INT_SWITCH3: PUSHC FLG FCLR I ; Disable interrupts AND.B #00H,0056H ; Set TRAIC register to 00h POPC FLG ; Enable interrupts
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 457 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.3 21.3.1
Notes on Timers Notes on Timer RA
* Timer RA stops counting after a reset. Set the values in the timer RA and timer RA prescalers before the *
count starts. Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by writing 0 to these bits by a program. However, these bits remain unchanged if 1 is written. When using the READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0 although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or TUNDF bit which is not supposed to be set to 0 with the MOV instruction. When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts. The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts. When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler immediately after the count starts, then set the TEDGF bit to 0. The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. Timer RA starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (during count). The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RA(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
*
* * * *
* When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
* When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 458 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.3.2
Notes on Timer RB
* Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts. * Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the MCU. Consequently, the timer value may be updated during the period when these two registers are being read. * In programmable one-shot generation mode and programmable wait one-shot generation mode, when setting the TSTART bit in the TRBCR register to 0 (count stops) or setting the TOSSP bit in the TRBOCR register to 1 (one-shot stops), the timer reloads the value of reload register and stops. Therefore, in programmable one-shot generation mode and programmable wait one-shot generation mode, read the timer count value before the timer stops. * The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to 1 (count starts) while the count is stopped. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bit is set to 0. During this time, do not access registers associated with timer RB(1) other than the TCSTF bit. NOTE: 1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and TRBPR.
* If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately. * If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elapsed. If the TOSSP bit is written to 1 during the period between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit may be set to either 0 or 1.
21.3.2.1
Timer mode
The following workaround should be performed in timer mode. To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: * When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. * When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 459 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.3.2.2
Programmable waveform generation mode
The following three workarounds should be performed in programmable waveform generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: * When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. * When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) To change registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), synchronize the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period A shown in Figures 21.2 and 21.3. The following shows the detailed workaround examples.
* Workaround example (a):
As shown in Figure 21.2, write to registers TRBSC and TRBPR in the timer RB interrupt routine. These write operations must be completed by the beginning of period A.
Period A
Count source/ prescaler underflow signal
TRBO pin output
Primary period
Secondary period
IR bit in TRBIC register
(a)
Interrupt request is acknowledged (b)
Ensure sufficient time
Interrupt request is generated
Instruction in Interrupt sequence interrupt routine
Set the secondary and then the primary register immediately
(a) Period between interrupt request generation and the completion of execution of an instruction. The length of time varies depending on the instruction being executed. The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as the divisor). (b) 20 cycles. 21 cycles for address match and single-step interrupts.
Figure 21.2
Workaround Example (a) When Timer RB interrupt is Used
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 460 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
* Workaround example (b):
As shown in Figure 21.3 detect the start of the primary period by the TRBO pin output level and write to registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A. If the port register's bit value is read after the port direction register's bit corresponding to the TRBO pin is set to 0 (input mode), the read value indicates the TRBO pin output value.
Period A
Count source/ prescaler underflow signal
TRBO pin output
Read value of the port register's bit corresponding to the TRBO pin (when the bit in the port direction register is set to 0)
Primary period
Secondary period
(i) (ii) (iii)
Ensure sufficient time
The TRBO output inversion is detected at the end of the secondary period.
Upon detecting (i), set the secondary and then the primary register immediately.
Figure 21.3
Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case, registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
21.3.2.3
Programmable one-shot generation mode
The following two workarounds should be performed in programmable one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: * When the TRBPRE register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the count source for each write interval. * When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 461 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.3.2.4
Programmable wait one-shot generation mode
The following three workarounds should be performed in programmable wait one-shot generation mode. (1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following points: * When the TRBPRE register is written continuously, allow three or more cycles of the count source for each write interval. * When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow for each write interval. (2) Do not set both the TRBPRE and TRBPR registers to 00h. (3) Set registers TRBSC and TRBPR using the following procedure. (a) To use "INT0 pin one-shot trigger enabled" as the count start condition Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before trigger input from the INT0 pin. (b) To use "writing 1 to TOSST bit" as the start condition Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the TRBPR register, allow an interval of 0.5 or more cycles of the count source before writing to the TOSST bit.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 462 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.3.3
Notes on Timer RD TRDSTR Register
21.3.3.1
* Set the TRDSTR register using the MOV instruction. * When the CSELi (i = 0 to 1) is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is written to the TSTARTi bit. * Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the CSELi bit is se to 0. * To stop counting by a program, set the TSTARTi bit after setting the CSELi bit to 1. Although the CSELi bit is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be stopped. * Table 21.1 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji (j = A, B, C, or D) pin with the timer RD output. Table 21.1 TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
TRDIOji Pin Output when Count Stops Hold the output level immediately before the count stops. Hold the output level after output changes by compare match.
Count Stop When the CSELi bit is set to 1, set the TSTARTi bit to 0 and the count stops. When the CSELi bit is set to 0, the count stops at compare match of registers TRDi and TRDGRAi.
21.3.3.2
TRDi Register (i = 0 or 1)
* When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register
is set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then write. If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to the TRDi register, the value is not written and the TRDi register is set to 0000h. These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi register. - 001b (Clear by the TRDi register at compare match with the TRDGRAi register.) - 010b (Clear by the TRDi register at compare match with the TRDGRBi register.) - 011b (Synchronous clear) - 101b (Clear by the TRDi register at compare match with the TRDGRCi register.) - 110b (Clear by the TRDi register at compare match with the TRDGRDi register.)
* When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV.W #XXXXh, TRD0 ;Writing JMP.B L1 ;JMP.B L1: MOV.W TRD0,DATA ;Reading
21.3.3.3
TRDSRi Register (i = 0 or 1)
When writing the value to the TRDSRi register and continuously reading the same register, the value before writing may be read. In this case, execute the JMP.B instruction between the writing and reading. Program example MOV.B #XXh, TRDSR0 ;Writing JMP.B L1 ;JMP.B L1: MOV.B TRDSR0,DATA ;Reading
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 463 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.3.3.4
Count Source Switch
* Switch the count source after the count stops. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register. * When changing the count source from fOCO40M to another source and stopping fOCO40M, wait 2 cycles
of f1 or more after setting the clock switch, and then stop fOCO40M. Change procedure (1) Set the TSTARTi (i = 0 or 1) bit in the TRDSTR register to 0 (count stops). (2) Change bits TCK2 to TCK0 in the TRDCRi register. (3) Wait 2 or more cycles of f1. (4) Set the FRA00 bit in the FRA0 register to 0 (high-speed on-chip oscillator stops).
21.3.3.5
Input Capture Function
* Set the pulse width of the input capture signal to 3 or more cycles of the timer RD operation clock (refer to
Table 14.11 Timer RD Operation Clocks). * The value in the TRDi register is transferred to the TRDGRji register 2 to 3 cycles of the timer RD operation clock after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = either A, B, C, or D) (no digital filter).
21.3.3.6
Reset Synchronous PWM Mode
* When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1. * Set to reset synchronous PWM mode by the following procedure:
Change procedure (1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 01b (reset synchronous PWM mode). (4) Set the other registers associated with timer RD again.
21.3.3.7
Complementary PWM Mode
* When complementary PWM mode is used for motor control, make sure OLS0 = OLS1. * Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure.
Change procedure: When setting to complementary PWM mode (including re-set), or changing the transfer timing from the buffer register to the general register in complementary PWM mode. (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode). (3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode). (4) Set the registers associated with other timer RD again. Change procedure: When stopping complementary PWM mode (1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops). (2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).
* Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.
When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation. However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register). The PWM period cannot be changed.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 464 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
* If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1,
in that order, when changing from increment to decrement operation. When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR register are set to 11b (complementary PWM mode, buffer data transferred at compare match between registers TRD0 and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to registers such as the TRDGRA0 register.
Count value in TRD0 register
m+1 Setting value in TRDGRA0 register m
Set to 0 by a program IMFA bit in TRDSR0 register 1 0 Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Not transferred from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 11b (transfer from the buffer register to the general register at compare match of between registers TRD0 and TRDGRA0). No change
Figure 21.4
Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 465 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
* The TRD1 register counts 1, 0, FFFFh, 0, 1, in that order, when changing from decrement to increment
operation. The UDF bit is set to 1 when changing between 1, 0, and FFFFh operation. Also, when bits CMD1 to CMD0 in the TRDFCR register are set to 10b (complementary PWM mode, buffer data transferred at underflow in the TRD1 register), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1). During FFFFh, 0, 1 operation, data are not transferred to registers such as the TRDGRB0 register. Also, at this time, the OVF bit remains unchanged.
Count value in TRD0 register
1
0
FFFFh Set to 0 by a program UDF bit in TRDSR0 register OVF bit in TRDSR0 register 1 0 1 0 Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Not transferred from buffer register When bits CMD1 to CMD0 in the TRDFCR register are set to 10b (transfer from the buffer register to the general register when the TRD1 register underflows). No change
Figure 21.5
Operation when TRD1 Register Underflows in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 466 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
* Select with bits CMD1 to CMD0 the timing of data transfer from the buffer register to the general register.
However, transfer takes place with the following timing in spite of the value of bits CMD1 to CMD0 in the following cases: Value in buffer register value in TRDGRA0 register: Transfer take place at underflow of the TRD1 register. After this, when the buffer register is set to 0001h or above and a smaller value than the value of the TRDGRA0 register, and the TRD1 register underflows for the first time after setting, the value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0.
n3 m+1 n2 n1 0000h Count value in TRD1 register Count value in TRD0 register
TRDGRD0 register
n2 Transfer
n3 Transfer n2 n3
n2 Transfer n2
n1 Transfer n1
TRDGRB0 register
n1
Transfer with timing set by bits CMD1 to CMD0
Transfer at underflow of TRD1 register because of n3 > m
Transfer at underflow of TRD1 register because of first setting to n2 < m
Transfer with timing set by bits CMD1 to CMD0
TRDIOB0 output
TRDIOD0 output
m: Value set in TRDGRA0 register The above applies under the following conditions: * Bits CMD1 to CMD0 in the TRDFCR register are set to 11b (data in the buffer register is transferred at compare match between registers TRD0 and TRDGRA0 in complementary PWM mode). * Both the OSL0 and OLS1 bits in the TRDFCR register are set to 1 (active `H" for normal-phase and counter-phase).
Figure 21.6
Operation when Value in Buffer Register Value in TRDGRA0 Register in Complementary PWM Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 467 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
When the value in the buffer register is set to 0000h: Transfer takes place at compare match between registers TRD0 and TRDGRA0. After this, when the buffer register is set to 0001h or above and a smaller value than the value of the TRDGRA0 register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time after setting, the value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD1 to CMD0.
m+1 n2 n1 0000h Count value in TRD1 register Count value in TRD0 register
TRDGRD0 register
n1 Transfer
0000h Transfer n1 0000h
n1 Transfer n1 Transfer
TRDGRB0 register
n2
Transfer with timing set by bits CMD1 to CMD0
Transfer at compare match between registers TRD0 and TRDGRA0 because content in TRDGRD0 register is set to 0000h
Transfer at compare match between registers TRD0 and TRDGRA0 because of first setting to 0001h n1 < m
Transfer with timing set by bits CMD1 to CMD0
TRDIOB0 output
TRDIOD0 output
m: Value set in TRDGRA0 register The above applies under the following conditions: * Bits CMD1 to CMD0 in the TRDFCR register are set to 10b (data in the buffer register is transferred at underflow of the TRD1 register in PWM mode). * Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active "H" for normal-phase and counter-phase).
Figure 21.7
Operation when Value in Buffer Register Is Set to 0000h in Complementary PWM Mode
21.3.3.8
Count Source fOCO40M
* The count source fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V. For supply voltage other
than that, do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b (select fOCO40M as the count source).
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 468 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.3.4
Notes on Timer RE Starting and Stopping Count
21.3.4.1
Timer RE has the TSTART bit for instructing the count to start or stop, and the TCSTF bit, which indicates count start or stop. Bits TSTART and TCSTF are in the TRECR1 register. Timer RE starts counting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to 1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit. Also, timer RE stops counting when setting the TSTART bit to 0 (count stops) and the TCSTF bit is set to 0 (count stops). It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0. During this time, do not access registers associated with timer RE other than the TCSTF bit. NOTE: 1. Registers associated with timer RE: TRESEC, TREMIN, TREHR, TREWK, TRECR1, TRECR2, and TRECSR.
21.3.4.2
Register Setting
Write to the following registers or bits when timer RE is stopped. * Registers TRESEC, TREMIN, TREHR, TREWK, and TRECR2 * Bits H12_H24, PM, and INT in TRECR1 register * Bits RCS0 to RCS3 in TRECSR register Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped). Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the TRECR2 register. Figure 21.8 shows a Setting Example in Real-Time Clock Mode.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 469 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
TSTART in TRECR1 = 0
Stop timer RE operation TCSTF in TRECR1 = 0?
TREIC00h (disable timer RE interrupt)
TRERST in TRECR1 = 1 Timer RE register and control circuit reset TRERST in TRECR1 = 0
Setting of registers TRECSR, TRESEC, TREMIN, TREHR, TREWK, and bits H12_H24, PM, and INT in TRECR1 register
Select clock output Select clock source Seconds, minutes, hours, days of week, operating mode Set a.m./p.m., interrupt timing
Setting of TRECR2
Select interrupt source
Setting of TREIC (IR bit0, select interrupt priority level)
TSTART in TRECR1 = 1 Start timer RE operation TCSTF in TRECR1 = 1?
Figure 21.8
Setting Example in Real-Time Clock Mode
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 470 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.3.4.3
Time Reading Procedure of Real-Time Clock Mode
In real-time clock mode, read registers TRESEC, TREMIN, TREHR, and TREWK when time data is updated and read the PM bit in the TRECR1 register when the BSY bit is set to 0 (not while data is updated). Also, when reading several registers, an incorrect time will be read if data is updated before another register is read after reading any register. In order to prevent this, use the reading procedure shown below.
* Using an interrupt
Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register in the timer RE interrupt routine.
* Monitoring with a program 1
Monitor the IR bit in the TREIC register with a program and read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the IR bit in the TREIC register is set to 1 (timer RE interrupt request generated).
* Monitoring with a program 2
(1) Monitor the BSY bit. (2) Monitor until the BSY bit is set to 0 after the BSY bit is set to 1 (approximately 62.5 ms while the BSY bit is set to 1). (3) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register after the BSY bit is set to 0.
* Using read results if they are the same value twice
(1) Read necessary contents of registers TRESEC, TREMIN, TREHR, and TREWK and the PM bit in the TRECR1 register. (2) Read the same register as (1) and compare the contents. (3) Recognize as the correct value if the contents match. If the contents do not match, repeat until the read contents match with the previous contents. Also, when reading several registers, read them as continuously as possible.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 471 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.4
Notes on Serial Interface
* When reading data from the UiRB (i = 0 or 1) register either in the clock synchronous serial I/O mode or in the
clock asynchronous serial I/O mode. Ensure the data is read in 16-bit units. When the high-order byte of the UiRB register is read, bits PER and FER in the UiRB register and the RI bit in the UiC1 register are set to 0. To check receive errors, read the UiRB register and then use the read data. Example (when reading receive buffer register): MOV.W 00A6H,R0 ; Read the U0RB register
* When writing data to the UiTB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units. Example (when reading transmit buffer register): MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 472 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.5 21.5.1
Notes on Clock Synchronous Serial Interface Notes on Clock Synchronous Serial I/O with Chip Select
Set the IICSEL bit in the PMR register to 0 (select clock synchronous serial I/O with chip select function) to use the clock synchronous serial I/O with chip select function.
21.5.2
Notes on I2C bus Interface
Set the IICSEL bit in the PMR register to 1 (select I2C bus interface function) to use the I2C bus interface.
21.5.2.1
Multimaster Operation
The following actions must be performed to use the I2C bus interface in multimaster operation.
* Transfer rate
Set the transfer rate by 1/1.8 or faster than the fastest rate of the other masters. For example, if the fastest transfer rate of the other masters is set to 400 kbps, the I2C-bus transfer rate in this MCU should be set to 223 kbps (= 400/1.18) or more.
* Bits MST and TRS in the ICCR1 register setting
(a) Use the MOV instruction to set bits MST and TRS. (b) When arbitration is lost, confirm the contents of bits MST and TRS. If the contents are other than the MST bit set to 0 and the TRS bit set to 0 (slave receive mode), set the MST bit to 0 and the TRS bit to 0 again.
21.5.2.2
Master Receive Mode
Either of the following actions must be performed to use the I2C bus interface in master receive mode. (a) In master receive mode while the RDRF bit in the ICSR register is set to 1, read the ICDRR register before the rising edge of the 8th clock. (b) In master receive mode, set the RCVD bit in the ICCR1 register to 1 (disables the next receive operation) to perform 1-byte communications.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 473 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.6
Notes on Hardware LIN
For the time-out processing of the header and response fields, use another timer to measure the duration of time with a Synch Break detection interrupt as the starting point.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 474 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.7
Notes on A/D Converter
* Write to each bit (other than bit 6) in the ADCON0 register, each bit in the ADCON1 register, or the SMP bit * * *
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF connected), wait for at least 1 s before starting the A/D conversion. After changing the A/D operating mode, select an analog input pin again. When using the one-shot mode, ensure that A/D conversion is completed before reading the AD register. The IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D conversion is completed. When using the repeat mode, select the frequency of the A/D converter operating clock AD or more for the CPU clock during A/D conversion. Do not select the fOCO-F for the AD. If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register. Connect 0.1 F capacitor between the P4_2/VREF pin and AVSS pin. Do not enter stop mode during A/D conversion. Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in wait mode) during A/D conversion.
*
*
* * *
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 475 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.8 21.8.1
Notes on Flash Memory CPU Rewrite Mode Operating Speed
21.8.1.1
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
21.8.1.2
Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference data in the flash memory: UND, INTO, and BRK.
21.8.1.3
Interrupts
Table 21.2 lists the EW0 Mode Interrupts, and Table 21.3 lists the EW1 Mode Interrupts. Table 21.2 EW0 Mode Interrupts
Mode
Status
When Maskable Interrupt Request is Acknowledged Any interrupt can be used by allocating a vector in RAM
EW0 During auto-erasure
Auto-programming
When Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Request is Acknowledged Once an interrupt request is acknowledged, auto-programming or auto-erasure is forcibly stopped immediately and the flash memory is reset. Interrupt handling starts after the fixed period and the flash memory restarts. Since the block during autoerasure or the address during autoprogramming is forcibly stopped, the normal value may not be read. Execute auto-erasure again and ensure it completes normally. Since the watchdog timer does not stop during the command operation, interrupt requests may be generated. Reset the watchdog timer regularly.
NOTES: 1. Do not use the address match interrupt while a command is being executed because the vector of the address match interrupt is allocated in ROM. 2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 476 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
Table 21.3
EW1 Mode Interrupts
Mode
Status
EW1 During auto-erasure (erase-suspend function enabled)
During auto-erasure (erase-suspend function disabled)
During autoprogramming (program suspend function enabled)
During autoprogramming (program suspend function disabled)
When Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 1, or Voltage Monitor 2 Interrupt Request is Acknowledged Auto-erasure is suspended after Once an interrupt request is acknowledged, auto-programming or td(SR-SUS) and interrupt auto-erasure is forcibly stopped handling is executed. Autoimmediately and the flash memory is erasure can be restarted by reset. Interrupt handling starts after the setting the FMR41 bit in the FMR4 register to 0 (erase restart) fixed period and the flash memory restarts. Since the block during autoafter interrupt handling erasure or the address during autocompletes. Auto-erasure has priority and the programming is forcibly stopped, the normal value may not be read. Execute interrupt request auto-erasure again and ensure it acknowledgement is put on completes normally. standby. Interrupt handling is Since the watchdog timer does not stop executed after auto-erasure during the command operation, completes. Auto-programming is suspended interrupt requests may be generated. Reset the watchdog timer regularly after td(SR-SUS) and interrupt using the erase-suspend function. handling is executed. Auto-programming can be restarted by setting the FMR42 bit in the FMR4 register to 0 (program restart) after interrupt handling completes. Auto-programming has priority and the interrupt request acknowledgement is put on standby. Interrupt handling is executed after auto-programming completes. When Maskable Interrupt Request is Acknowledged
NOTES: 1. Do not use the address match interrupt while a command is executing because the vector of the address match interrupt is allocated in ROM. 2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 477 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.8.1.4
How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt between writing 0 and 1.
21.8.1.5
Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be rewritten correctly. In this case, use standard serial I/O mode.
21.8.1.6
Program
Do not write additions to the already programmed address.
21.8.1.7
Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
21.8.1.8
Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 to 5.5 V as the supply voltage. Do not perform programming and erasure at less than 2.7 V.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 478 of 485
R8C/24 Group, R8C/25 Group
21. Usage Notes
21.9 21.9.1
Notes on Noise Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-up
Connect a bypass capacitor (at least 0.1 F) using the shortest and thickest write possible.
21.9.2
Countermeasures against Noise Error of Port Control Registers
During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers may be changed. As a firmware countermeasure, it is recommended that the port registers, port direction registers, and pull-up control registers be reset periodically. However, examine the control processing fully before introducing the reset routine as conflicts may be created between the reset routine and interrupt routines.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 479 of 485
R8C/24 Group, R8C/25 Group
22. Notes on On-Chip Debugger
22. Notes on On-Chip Debugger
When using the on-chip debugger to develop and debug programs for the R8C/24 Group and R8C/25 Group take note of the following. (1) (2) Do not access the related UART1 registers. Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be accessed by the user. Refer to the on-chip debugger manual for which areas are used. Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a user system. Do not use the BRK instruction in a user system. Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip debugger under less than 2.7 V is not allowed.
(3) (4) (5)
Connecting and using the on-chip debugger has some special restrictions. Refer to the on-chip debugger manual for details.
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 480 of 485
R8C/24 Group, R8C/25 Group
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website.
JEITA Package Code P-LQFP52-10x10-0.65 RENESAS Code PLQP0052JA-A Previous Code 52P6A-A MASS[Typ.] 0.3g
Under development
HD *1 39 D 27
40
26 bp b1
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
c1
c
Reference Dimension in Millimeters Symbol
14
1 ZD Index mark
13
ZE
52
Terminal cross section
A2
A
c
F
e
y
*3
L bp x Detail F L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
Nom 10.0 10.0 1.4 11.8 12.0 11.8 12.0 0.05 0.27 0.09 0
Min 9.9 9.9
Max 10.1 10.1
0.35
12.2 12.2 1.7 0.1 0.15 0.32 0.37 0.30 0.145 0.20 0.125 8 0.65 0.13 0.10 1.1 1.1 0.5 0.65 1.0
JEITA Package Code P-TFLGA64-6x6-0.65
RENESAS Code PTLG0064JA-A
Previous Code 64F0G
MASS[Typ.] 0.07g
A1
b1
S b
AB S AB
wSB
D
wSA A
e
H G F E
E
D C B A
Reference Dimension in Millimeters Symbol
x4 v Index mark (Laser mark)
yS
1
2
3
4
5
6
7
8
e
Index mark
D E v w A e b b1 x y
Nom Max 6.0 6.0 0.15 0.20 1.05 0.65 0.31 0.35 0.39 0.39 0.43 0.47 0.08 0.10
Min
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 481 of 485
R8C/24 Group, R8C/25 Group Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator
Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806), and Appendix Figure 2.2 shows a Connection Example with E8 Emulator (R0E000080KCE00).
TXD VCC
52 51 50 49 48 47 46 45 44 43 42 41 40
1 2 3
39 38 37
R8C/24 Group R8C/25 Group
4
36 35 34 33 32 31 30 29 28 27
MODE
5 6 7
RESET
8
Connect oscillation circuit(1) VSS
9 10 11 12 13
14 15 16 17 18
19
20
21
22
23
24
25
26
10 TXD 7 VSS
RXD 4 1 VCC
M16C flash starter (M3A-0806)
RXD NOTE: 1. An oscillation circuit must be connected, even when operating with the on-chip oscillator clock.
Appendix Figure 2.1
Connection Example with M16C Flash Starter (M3A-0806)
VCC
52 51 50 49 48 47 46 45 44 43 42 41 40
Open collector buffer 4.7k or more User logic
1 2 3
39 38 37
R8C/24 Group R8C/25 Group
4 5 6 7
36 35 34 33 32 31 30 29 28 27
Connect oscillation circuit(1)
14 12 10 8 VCC 6 4 2 VSS 13
8 9 10 11 12
4.7k 10% MODE
VSS
RESET
13
14 15 16 17 18 19 20 21 22 23 24 25 26
7 MODE
E8 emulator (R0E000080KCE00)
NOTE: 1. It is not necessary to connect an oscillation circuit when operating with the on-chip oscillator clock.
Appendix Figure 2.2
Connection Example with E8 Emulator (R0E000080KCE00)
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 482 of 485
R8C/24 Group, R8C/25 Group
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit.
VCC
52 51 50 49 48 47 46 45 44 43 42 41 40
1 2 3 4 5
39 38 37 36 35 34 33 32 31 30 29 28 27
14 15 16 17 18 19 20 21 22 23 24 25 26
R8C/24 Group R8C/25 Group
Connect oscillation circuit RESET Connect oscillation circuit VSS
6 7 8 9 10 11 12 13
NOTE: 1. After reset, the XIN and XCIN clocks stop. Write a program to oscillate the XIN and XCIN clocks.
Appendix Figure 3.1
Example of Oscillation Evaluation Circuit
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 483 of 485
R8C/24 Group, R8C/25 Group
Index
Index
[A] AD ....................................................................................... 386 ADCON0 ............................................................................. 385 ADCON1 ............................................................................. 386 ADCON2 ............................................................................. 386 ADIC .................................................................................... 106 AIER .................................................................................... 121 [C] CM0 ....................................................................................... 75 CM1 ....................................................................................... 76 CPSRF .................................................................................. 80 CSPR .................................................................................. 129 [F] FMR0 .................................................................................. 406 FMR1 .................................................................................. 407 FMR4 .................................................................................. 408 FRA0 ..................................................................................... 78 FRA1 ..................................................................................... 78 FRA2 ..................................................................................... 79 FRA4 ..................................................................................... 79 FRA6 ..................................................................................... 79 FRA7 ..................................................................................... 79 [I] ICCR1 ................................................................................. 338 ICCR2 ................................................................................. 339 ICDRR ................................................................................. 344 ICDRS ................................................................................. 344 ICDRT ................................................................................. 343 ICIER ................................................................................... 341 ICMR ................................................................................... 340 ICSR .................................................................................... 342 IICIC .................................................................................... 107 INT0IC ................................................................................. 108 INT1IC ................................................................................. 108 INTEN ................................................................................. 115 INTF .................................................................................... 116 [K] KIEN .................................................................................... 119 KUPIC ................................................................................. 106 [L] LINCR ................................................................................. 370 LINST .................................................................................. 371 [O] OCD ...................................................................................... 77 OFS ....................................................................... 27, 128, 401 [P] P2DRR .................................................................................. 58 PDi (i = 0 to 4 and 6) ............................................................. 56 Pi (i = 0 to 4 and 6) ................................................................ 56 PM0 ....................................................................................... 71 PM1 ....................................................................................... 71 PMR .............................................................. 58, 293, 314, 344 PRCR .................................................................................. 100 PUR0 ..................................................................................... 57 PUR1 .....................................................................................57 [R] RMAD0 ................................................................................121 RMAD1 ................................................................................121 [S] S0RIC ..................................................................................106 S0TIC ...................................................................................106 S1RIC ..................................................................................106 S1TIC ...................................................................................106 SAR ......................................................................................343 SSCRH ................................................................................308 SSCRL .................................................................................309 SSER ...................................................................................311 SSMR ...................................................................................310 SSMR2 .................................................................................313 SSRDR ................................................................................314 SSSR ...................................................................................312 SSTDR .................................................................................314 SSUIC ..................................................................................107 [T] TRA ......................................................................................136 TRACR .................................................................................135 TRAIC ..................................................................................106 TRAIOC .......................................135, 137, 140, 142, 144, 147 TRAMR ................................................................................136 TRAPRE ..............................................................................136 TRBCR .................................................................................151 TRBIC ..................................................................................106 TRBIOC ...............................................152, 154, 158, 160, 165 TRBMR ................................................................................152 TRBOCR ..............................................................................151 TRBPR .................................................................................153 TRBPRE ..............................................................................153 TRBSC .................................................................................153 TRD0 ............................................192, 207, 222, 233, 245, 258 TRD0IC ................................................................................107 TRD1 ............................................................192, 207, 222, 245 TRD1IC ................................................................................107 TRDCR0 ......................................188, 203, 219, 231, 242, 256 TRDCR1 ......................................................188, 203, 219, 242 TRDDF0 ...............................................................................187 TRDDF1 ...............................................................................187 TRDFCR ......................................186, 200, 217, 229, 240, 253 TRDGRAi (i = 0 to 1) ....................193, 208, 223, 234, 245, 259 TRDGRBi (i = 0 to 1) ....................193, 208, 223, 234, 245, 259 TRDGRCi (i = 0 to 1) ...................193, 208, 223, 234, 245, 259 TRDGRDi (i = 0 to 1) ...................193, 208, 223, 234, 245, 259 TRDIER0 ......................................192, 207, 221, 233, 244, 258 TRDIER1 ......................................192, 207, 221, 233, 244, 258 TRDIORA0 ...................................................................189, 204 TRDIORA1 ...................................................................189, 204 TRDIORC0 ...................................................................190, 205 TRDIORC1 ...................................................................190, 205 TRDMR ........................................184, 198, 215, 228, 239, 252 TRDOCR ..............................................................202, 219, 255 TRDOER1 ............................................201, 218, 230, 241, 254 TRDOER2 ............................................201, 218, 230, 241, 254 TRDPMR ..............................................................185, 199, 216 TRDPOCR0 .........................................................................222 TRDPOCR1 .........................................................................222 TRDSR0 .......................................191, 206, 220, 232, 243, 257
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 484 of 485
R8C/24 Group, R8C/25 Group
Index
TRDSR1 ...................................... 191, 206, 220, 232, 243, 257 TRDSTR ...................................... 184, 198, 215, 228, 238, 252 TRECR1 ...................................................................... 275, 282 TRECR2 ...................................................................... 276, 282 TRECSR ..................................................................... 277, 283 TREHR ................................................................................ 274 TREIC ................................................................................. 106 TREMIN ...................................................................... 273, 281 TRESEC ...................................................................... 273, 281 TREWK ............................................................................... 274 [U] U0BRG ................................................................................ 291 U0C0 ................................................................................... 292 U0C1 ................................................................................... 293 U0MR .................................................................................. 291 U0RB ................................................................................... 290 U0TB ................................................................................... 290 U1BRG ................................................................................ 291 U1C0 ................................................................................... 292 U1C1 ................................................................................... 293 U1MR .................................................................................. 291 U1RB ................................................................................... 290 U1SR ................................................................................... 293 U1TB ................................................................................... 290 [V] VCA1 ..................................................................................... 36 VCA2 ............................................................................... 36, 80 VW0C .................................................................................... 37 VW1C .................................................................................... 38 VW2C .................................................................................... 39 [W] WDC .................................................................................... 128 WDTR ................................................................................. 129 WDTS .................................................................................. 129
Rev.3.00 Feb 29, 2008 REJ09B0244-0300
Page 485 of 485
REVISION HISTORY REVISION HISTORY
Rev. 0.10 0.20 Date Jul 27, 2005 Jan 16, 2006
R8C/24 Group, R8C/25 Group Hardware Manual R8C/24 Group, R8C/25 Group Hardware Manual
Description
Page
-
Summary First Edition issued
all pages * "Preliminary" deleted * Symbol name "TRDMDR" "TRDMR", "SSUAIC" "SSUIC", "IIC2AIC" "IICIC", and "TSTOP0, TSTOP1" "CSEL0, CSEL1" revised * Pin name "TCLK" "TRDCLK" revised * Bit name "TPSC0 to TPSC2" "TCK0 to TCK2", "TRD0 count stop bit" "TRD0 count operation select bit", and "TRD1 count stop bit" "TRD1 count operation select bit" revised 2 3 4 Table 1.1 Functions and Specifications for R8C/24 Group revised Table 1.2 Functions and Specifications for R8C/25 Group revised Figure 1.1 Block Diagram; "Peripheral Functions" added, "System Clock Generation" "System Clock Generator" revised Table 1.3 Product Information for R8C/24 Group revised Table 1.4 Product Information of R8C/25 Group revised Figure 1.4 Pin Assignment (Top View); "VSS" "VSS/AVSS" and "VCC" "VCC/AVCC" revised Table 1.5 Pin Functions; "Analog power supply input" added, "Reference voltage input" revised Table 1.6 Pin Name Information by Pin Number "VSS" "VSS/AVSS" and "VCC" "VCC/AVCC" revised Figure 2.1 CPU Registers; "Reserved Area" "Reserved Bit" revised 2.8.10 Reserved Area; "Reserved Area" "Reserved bit" revised Figure 3.1 Memory Map of R8C/24 Group; "Program area" "program ROM" revised 3.2 R8C/25 Group, Figure 3.2 Memory Map of R8C/25 Group; "Data area" "data flash", "Program area" "program ROM" revised Table 4.1 SFR Information(1); 0012h: "X0h" "00h" 0016h: "X0h" "00h" 0024h: "TBD" "When shipping" NOTES 3 and 4 revised Figure 5.4 OFS Register; NOTE1 revised and NOTE3 added 5.1.1 When Power Supply is Stable (2) revised 5.1.2 Power On (4) revised Figure 5.5 Example of Hardware Reset Circuit and Operation and Figure 5.6 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation revised
5 6 7 8 9 10 12 13 14 15
24 25 26
C-1
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 0.20
Date Jan 16, 2006
Page 27 28
Summary 5.2 Power-On Reset Function "When a capacitor is ... or more." added Figure 5.7 Example of Power-On Reset Circuit and Operation revised 5.4 Voltage Monitor 1 Reset; "When ... VCC pin drops the Vdet1 ..." "When ... VCC pin reaches to the Vdet1 ..." revised "6. Programmable I/O Ports" "6. Voltage Detection Circuit" and "7. Voltage Detection Circuit" "7. Programmable I/O Ports" revised Figure 6.5 Registers VCA1 and VCA2; VCA2 register revised Figure 6.6 VW0C Register revised Figure 7.2 Configuration of Programmable I/O Ports (2) revised Figure 7.3 Configuration of Programmable I/O Ports (3) revised Figure 7.5 Configuration of Programmable I/O Ports (5) revised Figure 7.6 Configuration of Programmable I/O Ports (6) revised Figure 7.7 Configuration of Programmable I/O Ports (7) revised 7.4 Port setting added; Table 7.4 Port P0_0/AN7 to Table 7.47 Port P6_7/INT3/RXD1 added Table 7.48 Unassigned Pin Handling revised 9. Bus revised; "However, only following SFRs are ... accessed at a time." added Table 9.2 Bus Cycles by Access Space of the R8C/25 Group added, Table 9.3 Access Unit and Bus Operations; "SFR" "SFR, data flash", "ROM/RAM" "ROM (program ROM), RAM" revised Figure 10.1 Clock Generation Circuit revised Figure 10.2 CM0 Register revised Figure 10.3 CM1 Register revised Figure 10.5 Registers FRA0 and FRA1; FRA0 register revised Figure 10.8 VCA2 Register added Figure 10.9 Examples of XIN Clock Connection Circuit revised 10.2.2 High-Speed On-Chip Oscillator Clock; "To use the high-speed on-chip ... or more)." added 10.3 XCIN Clock "To input an external clock ... pin open." added 10.4.2 CPU Clock "Use the XCIN clock while ... stabilizes." added 10.4.3 Peripheral Function Clock (f1, f2, f4, f8, f32, fC4, and fC32); "Use fC4 and fC32 while the XCIN clock oscillation stabilizes." added 10.4.5 fOCO40M; "fOCO40M can be ... supply voltage VCC = 3.0 to 5.5 V." added 10.4.8 fOCO128 added Table 10.2 Settings and Modes of Clock Associated Bits revised
30 to 67 33 34 46 47 49 50 51 56 to 66 67 69
71 72 73 75 77 78 79 80 81
82
C-2
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 0.20
Date Jan 16, 2006
Page 83
Summary 10.5.1.2 Low-Speed Clock Mode; "In this mode, stopping the XIN clock ... the VCA20 bit." added 10.5.1.4 Low-Speed On-Chip Oscillator Mode; "In this mode, stopping the XIN clock ... the VCA20 bit." added Figure 10.11 Handling Procedure of Internal Power Low Consumption Enabled by VCA20 bit added Figure 10.12 State Transition in Power Control Mode revised 10.6.1 How to Use Oscillation Stop Detection Function; "* This function cannot be... is 2 MHz or below. ..." "* This function cannot be... is below 2 MHz. ..." revised 10.7.1 Stop Mode and 10.7.2 Wait Mode 10.7.1 Stop Mode and Wait Mode revised 10.7.3 Oscillation Stop Detection Function; "Since ... is 2 MHz or below, ..." "Since ... is below 2 MHz. ..." revised "To use this MCU with supply voltage ... to the chip externally." added 10.7.4 fOCO40M added Figure 12.11 Interrupt Priority Level Judgement Circuit; NOTE2 deleted Figure 12.18 Registers AIER and RMAD0 to RMAD1; AIER and RMAD0 to RMAD1 register revised 12.6.7 Entering Wait Mode after Oscillation Stop Detection Interrupt is Detected added Figure 13.2 Registers OFS and WDC; OFS register NOTE1 revised and NOTE3 added, and WDC register NOTE1 deleted Table 14.1 Functional Comparison of Timers; Input Pin: Timer RD "TRDCLK" added Figure 14.1 Block Diagram of Timer RA revised Table 14.3 Pulse Output Mode Specifications revised Table 14.6 Pulse Period Measurement Mode Specifications revised
Figure 14.11 Operating Example of Pulse Period Measurement Mode revised
84 88 89
92
107 114 119 121 126 127 135 142 144 146 147 149 158
Figure 14.12 Block Diagram of Timer RB revised
Figure 14.13 Registers TRBCR and TRBOCR; TRBOCR register revised
Figure 14.15 Registers TRBPRE, TRBSC, and TRBPR; TRBPR register revised Figure 14.20 TRBIOC Register in Programmable One-Shot Generation Mode Figure 14.23 Registers TRBIOC and TRBMR in Programmable OneShot Generation Mode; TRBIOC register NOTE2 revised Figure 14.25 Registers TRBIOC and TRBMR in Programmable Wait One-Shot Generation Mode; TRBIOC register NOTE2 revised -Output compare function; "(Pin output can be changed at detection)" added
162 165
C-3
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 0.20
Date
Page
Summary
Jan 16, 2006 166 to 168 Tables 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0) Tables 14.13 Pin Functions TRDIOB0(P2_1) Tables 14.14 Pin Functions TRDIOC0(P2_2) Tables 14.15 Pin Functions TRDIOD0(P2_3) Tables 14.16 Pin Functions TRDIOA1(P2_4) Tables 14.17 Pin Functions TRDIOB1(P2_5) Tables 14.18 Pin Functions TRDIOC1(P2_6) Tables 14.19 Pin Functions TRDIOD1(P2_7) Tables 14.20 Pin Functions INT0(P4_5) added 170 170 14.3.1 Mode Selection deleted Table 14.21 Count Source Selection revised 14.3.1 Count Sources; "TRDCRi register to ..." "TRDCRi register (i = 0 or 1) to ..." revised Figure14.29 Buffer Operation in Input Capture Function revised Figure14.30 Buffer Operation in Output Capture Function revised 14.3.2 Buffer Operation; "input capture and ..." "timer mode (input capture and ..." "the IOC2 to IOC0 bits in ..." "the IOC2 bit in ..." "the IOA2 to IOA0 bits in ..." "the IOA2 bit in ..." "the IOD2 to IOD0 bits in ..." "the IOD2 bit in ..." "the IOB2 to IOC0 bits in ..." "the IOB2 bit in ..." revised "Bits IMFC and IMFD in the TRDSRi...input capture function." added 14.3.3 Synchronous Operation; "For the synchronous operation, ... register = 110b)." deleted 14.3.4 Pulse Output Forced Cutoff; "P2D" "PD2", "P4D" "PD4", and "P4_5" "PD4_5", revised "According to the selection ... details of interrupts." added 14.3.5 Input Capture Function; "The TRDGRA0 register can also ... trigger input." added Figure 14.33 Block Diagram of Input Capture Function revised Table 14.23 Specifications of Input Capture Function revised Figure 14.34 Registers TRDSTR and TRDMR in Input Capture Function revised Figure 14.35 TRDPMR Register in Input Capture Function revised Figure 14.36 TRDFCR Register in Input Capture Function revised Figure 14.39 Registers TRDIORA0 to TRDIORA1 in Input Capture Function revised Figure 14.40 Registers TRDIORC0 to TRDIORC1 in Input Capture Function revised Figure 14.41 Registers TRDSR0 to TRDSR1 in Input Capture Function revised Table 14.25 Input Pin Function in Input Capture Function deleted 14.3.5.1 Digital Filter; "TRDDF register ..." "TRDDFi register ..." revised C-4
171 172
173 174
176
177 178 179 180 183 184 185 187 189
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 0.20
Date Jan 16, 2006
Page 192 193 194 195
Summary Figure 14.48 Registers TRDSTR and TRDMR in Output Compare Function revised Figure 14.49 TRDPMR Register in Output Compare Function revised Figure 14.50 TRDFCR Register in Output Compare Function revised Figure 14.51 Registers TRDOER1 to TRDOER2 in Output Compare Function; TRDOER2 register: NOTE1 added Figure 14.54 Registers TRDIORA0 to TRDIORA1 in Output Compare Function revised Figure 14.55 Registers TRDIORC0 to TRDIORC1 in Output Compare Function revised Figure 14.56 Registers TRDSR0 to TRDSR1 in Output Compare Function revised Figure 14.64 Registers TRDSTR and TRDMR in PWM Mode revised Figure 14.65 TRDPMR Register in PWM Mode revised Figure 14.66 TRDFCR Register in PWM Mode revised Figure 14.67 Registers TRDOER1 to TRDOER2 in PWM Mode; TRDOER2 register: NOTE1 added Figure 14.69 Registers TRDSR0 to TRDSR1 in PWM Mode revised Figure 14.77 Registers TRDSTR to TRDMR in Reset Synchronous PWM Mode revised Figure 14.78 TRDFCR Register in Reset Synchronous PWM Mode revised Figure 14.79 Registers TRDOER1 to TRDOER2 in Reset Synchronous PWM Mode; TRDOER2 register: NOTE1 added Figure 14.81 Registers TRDSR0 to TRDSR1 in Reset Synchronous PWM Mode revised Figure 14.87 TRDSTR Register in Complementary PWM Mode revised Figure 14.88 TRDMR Register in Complementary PWM Mode revised Figure 14.89 TRDFCR Register in Complementary PWM Mode revised Figure 14.90 Registers TRDOER1 to TRDOER2 in Complementary PWM Mode; TRDOER2 register: NOTE1 added Figure 14.92 Registers TRDSR0 to TRDSR1 in Complementary PWM Mode revised Figure 14.98 Block Diagram of PWM3 Mode revised Table 14.33 Specifications of PWM3 Mode revised Figure 14.99 TRDSTR Register in PWM3 Mode revised Figure 14.100 TRDMR Register in PWM3 Mode revised Figure 14.101 TRDFCR Register in PWM3 Mode revised
198 199 200 209 210 211 212 214 222 223 224
226 232 233 234 235
237 244 245 246 247 248
C-5
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 0.20
Date Jan 16, 2006
Page 249 251 252 253 255 256 259 260 264 275 281 285 286 287 295 300 358
Summary Figure 14.102 Registers TRDOER1 to TRDOER2 in PWM3 Mode; TRDOER2 register: NOTE1 added Figure 14.104 TRDCR0 Register in PWM3 Mode NOTE1 deleted Figure 14.105 TRDSR0 Register in PWM3 Mode revised Figure 14.106 TRDIER0 Register in PWM3 Mode revised Table 14.34 TRDGRji Register Functions in PWM3 Mode revised Figure 14.109 Operating Example of PWM3 Mode revised 14.3.12.1 TRDSTR Register (i = 0 or 1) added 14.3.12.4 "Count Clock Source Switch" "Count Source Switch" revised 14.3.12.9 Count Source fOCO40M added Table 14.39 Output Compare Mode Specifications revised Figure 14.132 Setting Example in Real-Time Clock Mode revised Figure 15.3 Registers U0TB to U1TB and U0RB to U1RB revised Figure 15.4 Registers U0BRG to U1BRG and U0MR to U1MR; U0BRG to U1BRG register revised Figure 15.5 Registers U0C0 to U1C0 NOTE1 added Table 15.5 Registers Used and Settings for UART Mode; UiBRG: "-" "0 to 7" revised Table 16.1 Mode Selections revised Figure 16.46 Example of Register Setting in Master Transmit Mode (Clock Synchronous Serial Mode); "* Set the IICSEL bit in the PMR register to 1" added Table 18.1 Performance of A/D converter revised Figure 18.1 Block Diagram of A/D Converter; "VSS" "AVSS" and "Vref" "Vcom" revised 18.7 Notes on A/D Converter "* Connect 0.1F capacitor ... VSS pin." "* Connect 0.1F capacitor ... AVSS pin." revised Table 19.1 Flash Memory Version Performance; * Program and Erase Endurance:(Program area) (Program ROM), (Data area) (Data flash) revised * NOTE3 added 19.2 Memory Map; "The user ROM ... area ... Block A and B." "The user ROM ... area (program ROM) ... Block A and B (data flash)." revised Figure 19.1 Flash Memory Block Diagram for R8C/24 Group revised Figure 19.2 Flash Memory Block Diagram for R8C/25 Group revised Figure 19.4 OFS Register; NOTE1 revised and NOTE3 added 19.4.2.4 FMSTP Bit revised C-6
377 378
387 to 389 18.4 A/D Conversion Cycles to 18.6 Inflow Current Bypass Circuit added 390
391
392
393 395 398
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 0.20
Date Jan 16, 2006
Page 399 402 405 19.4.2.16 FMR47 Bit revised
Summary Figure 19.7 FMR4 Register NOTE4 revised Figure 19.11 Process to Reduce Power Consumption in High-Speed OnChip Oscillator Mode, Low-Speed On-Chip Oscillator Mode (XIN Clock Stops) and Low-Speed Clock Mode (XIN Clock Stops) revised 19.4.3.5 Block Erase; "The block erase command cannot be ... program-suspend." added Figure 19.14 Block Erase Command (When Using Erase-Suspend Function) revised Figure 19.15 Full Status Check and Handling Procedure for Individual Errors revised Figure 19.16 Pin Connections for Standard Serial I/O Mode revised 19.7.1.9 Program and Erase Voltage for Flash Memory added Table 20.1 Absolute Maximum Ratings; "VCC" "VCC/AVCC" revised Table 20.2 Recommended Operating Conditions revised Table 20.3 A/D Converter Characteristics revised Table 20.4 Flash Memory (Program ROM) Electrical Characteristics revised Table 20.5 Flash Memory (Data flash Block A, Block B) Electrical revised Table 20.6 Voltage Detection 0 Circuit Electrical Characteristics revised Table 20.7 Voltage Detection 1 Circuit Electrical Characteristics revised Table 20.8 Voltage Detection 2 Circuit Electrical Characteristics revised Table 20.9 Reset Circuit Electrical Characteristics (When Using Voltage Monitor 0 Reset) NOTE2 revised Table 20.11 High-speed On-Chip Oscillator Circuit Electrical Characteristics revised Table 20.12 Low-speed On-Chip Oscillator Circuit Electrical Characteristics revised Table 20.13 Power Supply Circuit Timing Characteristics revised Table 20.14 Timing Requirements of Clock Synchronous Serial I/O with Chip Select revised Table 20.15 Timing Requirements of I2C bus Interface NOTE1 revised Table 20.16 Electrical Characteristics (1) [VCC = 5 V] revised Table 20.17 Electrical Characteristics (2) [VCC = 5 V] revised Table 20.18 XIN Input, XCIN Input revised Table 20.20 Serial Interface revised Table 20.22 Electrical Characteristics (3) [VCC = 3 V] revised Table 20.23 Electrical Characteristics (4) [Vcc = 3 V] revised Table 20.24 XIN Input, XCIN Input revised Table 20.26 Serial Interface revised Table 20.28 Electrical Characteristics (5) [VCC = 2.2 V] revised C-7
408 409 412 414 419 420
421 422 423 424
425 426
427 431 432 433 434 435 436 437 438 439 440
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 0.20
Date Jan 16, 2006
Page 441 442 443 444
Summary Table 20.29 Electrical Characteristics (6) [Vcc = 2.2 V] revised Table 20.30 XIN Input, XCIN Input revised Table 20.31 TRAIO Input, INT1 Input revised Table 20.32 Serial Interface revised Table 20.33 External Interrupt INTi (i = 0, 2, 3) Input 21.1.1 Stop Mode and 21.1.2 Wait Mode 21.1.1 Stop Mode and Wait Mode revised 21.1.3 Oscillation Stop Detection Function; "Since ... is 2 MHz or below, ..." "Since ... is below 2 MHz. ..." revised "To use this MCU with supply voltage ... to the chip externally." added 21.1.4 fOCO40M added 21.2.7 Entering Wait Mode after Oscillation Stop Detection Interrupt is Detected added 21.7 Notes on A/D Converter "* Connect 0.1F capacitor ... VSS pin." "* Connect 0.1F capacitor ... AVSS pin." revised 21.8.1.9 Program and Erase Voltage for Flash Memory added 22. Notes for On-Chip Debugger; (1) and (6) added, "(2) Do not use addresses ... addresses." deleted Appendix 1. Package Dimensions; "TBD" "PLQP0052JA-A (52P6A-A)" added Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806) revised Appendix Figure 2.2 Connection Example with E8 Emulator (R0E000080KCE00) revised Appendix Figure 3.1 Example of Oscillation Evaluation Circuit revised Table 1.2 Functions and Specifications for R8C/25 Group revised Figure 1.1 Block Diagram; "System clock generator" "System clock generation circuit" revised Table 1.3 Product Information for R8C/24 Group and Table 1.4 Product Information for R8C/25 Group; A part of (D) mark is deleted. Table 1.6 Pin Name Information by Pin Number NOTE1 added Table 4.1 SFR Information(1); 001Ch: "00h" "00h, 10000000b" revised 0029h: High-Speed On-Chip Oscillator Control Register 4 FRA4 When shipping added 002Bh: High-Speed On-Chip Oscillator Control Register 6 FRA6 When shipping added NOTE6 added Table 4.5 SFR Information(5); 0118h: Timer RE Second Data Register / Counter Data Register, 0119h: Timer RE Minute Data Register / Compare Data Register register name revised
447 462
465 467 468 469
470 1.00 May 31, 2006 3 4 5 to 6 9 15
all pages "Under development" deleted
19
C-8
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 1.00
Date May 31, 2006
Page 20 24 25 26
Summary Table 4.6 SFR Information(6); 0143h: "11000000b" "11100000b" revised Figure 5.4 OFS Register NOTE2 revised 5.1.1 When Power Supply is Stable (2) revised 5.1.2 Power On (4) revised Figure 5.5 Example of Hardware Reset Circuit and Operation and Figure 5.6 Example of Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation revised Figure 5.7 Example of Power-On Reset Circuit and Operation revised 5.3 Voltage Monitor 0 Reset revised Figure 6.5 Registers VCA1 and VCA2; VCA2 register NOTE6 revised
Figures 7.1 to .7.7 Configuration of Programmable I/O Ports NOTE1 added
27 28 33 45 to 51 53 54 62 70 71 72 74 75 76 77 78 79 81 82 83 84 85 86
Figure 7.9 PDi (i = 0 to 4 and 6) Registers NOTE3 added Figure 7.11 Registers PUR0 and PUR1; After Reset revised Table 7.31 Port P3_4/SDA/SCS revised Table 10.1 Specifications of Clock Generation Circuit revised Figure 10.1 Clock Generation Circuit revised Figure 10.2 CM0 Register; NOTE6 deleted and NOTE9 revised Figure 10.4 OCD Register revised Figure 10.5 Registers FRA0 and FRA1; FRA0 register NOTE2 revised Figure 10.6 Registers FRA2, FRA4, and FRA6; FRA2 register NOTE2 deleted, registers FRA4 and FRA6 added Figure 10.8 VCA2 Register NOTE6 revised Figure 10.9 Examples of XIN Clock Connection Circuit NOTE1 revised 10.2.2 High-Speed On-Chip Oscillator Clock revised 10.4.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) revised 10.4.9 fC4 and fC32 added Table 10.2 Settings and Modes of Clock Associated Bits revised 10.5.1.2 Low-Speed Clock Mode revised 10.5.2.2 Entering Wait Mode and 10.5.2.3 Pin Status in Wait Mode revised 10.5.2.4 Exiting Wait Mode; "When using a peripheral ...instruction is executed." page changed Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions revised 10.5.2.4 Exiting Wait Mode; "When exiting by a peripheral ... CPU clock supply is started." "When exiting by a peripheral ... CM07 bit in the CM0 register." revised Figure 10.11 Time between Wait Mode and Interrupt Routine Execution added 10.5.2.5 Reducing the Internal Power Consumption added Figure 10.12 Handling Procedure of Internal Power Low Consumption Enabled by VCA20 bit revised
87
88
C-9
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 1.00
Date May 31, 2006
Page 89 90 92 93 94
Summary Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions revised Figure 10.13 Time between Stop Mode and Interrupt Routine Execution added 10.6.1 How to Use Oscillation Stop Detection Function revised Figure 10.15 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN Clock revised Figure 10.16 Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt revised 10.7.1 Stop Mode and Wait Mode revised and 10.7.4 fOCO40M deleted Figure 12.1 Interrupts revised Table 12.5 IPL Value When Software or Special Interrupt Is Acknowledged revised Figure 12.10 Priority Levels of Hardware Interrupts revised 12.6.7 Entering Wait Mode after Oscillation Stop Detection Interrupt is Detected deleted Figure 13.1 Block Diagram of Watchdog Timer revised Figure 13.2 Registers OFS and WDC; OFS Register NOTE2 revised 14. Timers; "The count source for each timer ... and reloading." deleted 14.1 Timer RA; "The count source for timer RA ... and reloading." added Figure 14.1 Block Diagram of Timer RA revised Figure 14.2 Registers TRACR and TRAIOC revised Figure 14.3 Registers TRAMR, TRAPRE, and TRA revised Table 14.2 Timer Mode Specifications revised Figure 14.4 TRAIOC Register in Timer Mode revised (Figure 14.4 TRACR Register in Timer Mode deleted, Figure 14.5 Registers TRAIOC and TRAMR in Timer Mode TRAMR register deleted) 14.1.1.1 Timer Write Control during Count added Figure 14.5 Operating Example of Timer RA when Count Value is Rewritten during Count added Table 14.3 Pulse Output Mode Specifications revised Figure 14.6 TRAIOC Register in Pulse Output Mode revised (Figure 14.6 Registers TRACR and TRAIOC in Pulse Output Mode TRACR register deleted, Figure 14.7 TRAMR Register in Pulse Output Mode deleted) Table 14.4 Event Counter Mode Specifications revised Figure 14.7 TRAIOC Register in Event Counter Mode revised (Figure 14.8 Registers TRACR and TRAIOC in Event Counter Mode TRACR register deleted, Figure 14.9 TRAMR Register in Event Counter Mode deleted) Table 14.5 Pulse Width Measurement Mode Specifications revised
95 97 107 109 122 123 124 128 130 131 132 133
134
135 136
137 138
139
C - 10
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 1.00
Date May 31, 2006
Page 140
Summary
Figure 14.8 TRAIOC Register in Pulse Width Measurement Mode revised (Figure 14.10 Registers TRACR and TRAIOC in Pulse Width Measurement Mode TRACR register deleted, Figure 14.11 TRAMR Register in Pulse Width Measurement Mode deleted) Figure 14.9 Operating Example of Pulse Width Measurement Mode revised
141 142 143
Table 14.6 Pulse Period Measurement Mode Specifications revised
Figure 14.10 TRAIOC Register in Pulse Period Measurement Mode revised (Figure 14.13 Registers TRACR and TRAIOC in Pulse Period Measurement Mode TRACR register deleted, Figure 14.14 TRAMR Register in Pulse Period Measurement Mode deleted) Figure 14.11 Operating Example of Pulse Period Measurement Mode revised
144 146
14.2 Timer RB; "The count source for timer RB ... and reloading." added * Timer mode: ... (peripheral function clock ... added Figure 14.12 Block Diagram of Timer RB revised Figure 14.13 Registers TRBCR and TRBOCR revised Figure 14.14 Registers TRBIOC and TRBMR revised Figure 14.15 Registers TRBPRE, TRBSC, and TRBPR revised Table 14.7 Timer Mode Specifications revised Figure 14.16 TRBIOC Register in Timer Mode revised (Figure 14.20 Registers TRBIOC and TRBMR in Timer Mode TRBMR register deleted) 14.2.1.1 Timer Write Control during Count added Figure 14.17 Operating Example of Timer RB when Count Value is Rewritten during Count added Table 14.8 Programmable Waveform Generation Mode Specifications revised Figure 14.18 TRBIOC Register in Programmable Waveform Generation Mode revised (Figure 14.20 Registers TRBIOC and TRBMR in Timer Mode TRBMR register deleted) Figure 14.19 Operating Example of Timer RB in Programmable Waveform Generation Mode revised
Table 14.9 Programmable One-Shot Generation Mode Specifications revised
147 148 149 150
151 152 153 154
155 156
Figure 14.20 TRBIOC Register in Programmable One-Shot Generation Mode revised (Figure 14.23 Registers TRBIOC and TRBMR in Programmable OneShot Generation Mode TRBMR register deleted) Figure 14.21 Operating Example of Programmable One-Shot Generation Mode revised 14.2.3.1 Selecting One-shot Trigger added Table 14.10 Programmable Wait One-Shot Generation Mode Specifications revised
157 158 159
C - 11
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 1.00
Date May 31, 2006
Page 161
Summary Figure 14.22 TRBIOC Register in Programmable Wait One-Shot Generation Mode (Figure 14.25 Registers TRBIOC and TRBMR in Programmable Wait One-Shot Generation Mode TRBMR register deleted) Figure 14.23 Operating Example of Programmable Wait One-Shot Generation Mode revised 14.2.5 Notes on Timer RB; "* ... Timer RB starts counting at the first ... 1 (during count)." deleted "* When the TSTOP bit in the TRBCR register ... immediately stops. * If the TOSST bit or the TOSSP bit ... also be set to 0 or 1." added Table 14.12 Pin Functions TRDIOA0/TRDCLK(P2_0) revised Table 14.20 Pin Functions INT0(P4_5) revised
Figure 14.33 TRDFCR Register in Input Capture Function NOTE2 revised Figure 14.47 TRDFCR Register in Output Compare Function NOTE2 revised
162 163
165 167 179 193 210 220 222 225 227 233 239 244 247 254 258 259
Figure 14.63 TRDFCR Register in PWM Mode NOTE2 revised Table 14.29 Reset Synchronous PWM Mode Specifications revised Figure 14.75 TRDFCR Register in Reset Synchronous PWM Mode NOTES 1 and 3 revised Figure 14.78 Registers TRDSR0 to TRDSR1 in Reset Synchronous PWM Mode revised Table 14.30 TRDGRji Register Functions in Reset Synchronous PWM Mode revised Figure 14.86 TRDFCR Register in Complementary PWM Mode NOTES 1 and 4 revised 14.3.9 Complementary PWM Mode; "Since a value cannot be written to ... BFC1, and BFD1." added Table 14.33 Specifications of PWM3 Mode revised Figure 14.98 TRDFCR Register in PWM3 Mode NOTE2 revised Table 14.34 TRDGRji Register Functions in PWM3 Mode revised, 14.3.10 PWM3 Mode; "Registers TRDGRC0, ... and BFD1." added 14.3.12.1 TRDSTR Register (i = 0 or 1); "* Table 14.36 lists the TRDIOji (j = A, B, C, ... timer RD output." added
14.3.12.6 Reset Synchronous PWM Mode; Change procedure (2) revised 14.3.12.7 Complementary PWM Mode; *Change bits CMD1 to CMD0 in the TRDFCR register in the ... ; Change procedure: When setting to complementary ... (2) , Change procedure: When stopping complementary ... (1) and (2) revised *Do not write to ... ; "However, set to the TRDGRD0, ... BFD1." added
263 264 265
14.3.12.8 PWM3 Mode deleted 14.4 Timer RE; "The count source for timer RE ... operations." added Figure 14.112 Block Diagram of Real-Time Clock Mode revised
C - 12
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 1.00
Date May 31, 2006
Page 287 288 289 294 296 300 304 307 308 309 314 316 319 320 322 323 358
Summary Figure 15.6 Registers U0C1 to U1C1, U1SR, and PMR; U0C1 to U1C1 register NOTE2 added Table 15.1 Clock Synchronous Serial I/O Mode Specifications revised
15.1 Clock Synchronous Serial I/O Mode; "Table 15.3 ... The TXD0 pin ..." "Table 15.3 ... The TXDi pin ..." revised 15.2 Clock Asynchronous Serial I/O (UART) Mode; "Table 15.6 ... The TXD0 pin ..." "Table 15.6 ... The TXDi pin ..." revised
Figure 15.11 Receive Timing Example in UART Mode; "RI bit" "IR bit" revised Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications; "" "f1" revised and NOTE2 deleted Figure 16.4 SSMR Register Figure 16.7 SSMR2 Register revised
Figure 16.8 Registers SSTDR and SSRDR; SSTDR registers NOTE1 deleted
16.2.1 Transfer Clock; "" "f1" revised 16.2.5.2 Data Transmission; "When setting the MCU is set as a slave device, ... enabled." deleted Figure 16.14 Sample Flowchart of Data Transmission (Clock Synchronous Communication Mode) NOTE2 deleted 16.2.5.4 Data Transmission/Reception; "When the MCU is set as the slave device, ... enabled." deleted Figure 16.17 Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication Mode) NOTE2 deleted Figure 16.18 Initialization in 4-Wire Bus Communication Mode revised 16.2.6.2 Data Transmission; "When the MCU is set as a slave device, ... enabled." deleted Figure 16.47 Example of Register Setting in Master Receive Mode (I2C bus Interface Mode) revised
362 to 375 17. Hardware LIN; "Sync Break" "Synch Break" and "Sync Field" "Synch Field" revised 362 364 365 366 367 368 369 370 371 Figure 17.1 Block Diagram of Hardware LIN revised Figure 17.2 LINCR Register revised Figure 17.3 LINST Register revised Figure 17.4 Typical Operation when Sending a Header Field "RAIC" "TRAIC" revised
Figure 17.5 Example of Header Field Transmission Flowchart (1) revised Figure 17.6 Example of Header Field Transmission Flowchart (2) revised
17.4.2 Slave Mode (5) revised Figure 17.7 Typical Operation when Receiving a Header Field revised Figure 17.8 Example of Header Field Reception Flowchart (1) revised Figure 17.9 Example of Header Field Reception Flowchart (2) revised
C - 13
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 1.00
Date May 31, 2006
Page 372 373 374
Summary Figure 17.10 Example of Header Field Reception Flowchart (3) revised Figure 17.11 Typical Operation when a Bus Collision is Detected; "RAIC" "TRAIC" revised 17.5 Interrupt Requests; "There are four ... Sync Break generation completed, ... , and bus collision detection." "There are three ... , and bus collision detection." revised Table 17.2 Interrupt Requests of Hardware LIN revised Table 18.1 Performance of A/D converter revised Table 18.2 One-Shot Mode Specifications revised Figure 18.6 ADCON0 Register in Repeat Mode revised 18.3 Sample and Hold; "... to 28 AD cycles for 8-bit resolution or 33 AD resolution" and "When performing A/D conversion, charge the sampling time." deleted Figure 18.10 Internal Equivalent Circuit of Analog Input revised 18.6 Inflow Current Bypass Circuit deleted 18.6 Output Impedance of Sensor under A/D Conversion added 18.7 Notes on A/D Converter revised Figure 19.4 OFS Register NOTE2 revised Table 19.3 Differences between EW0 Mode and EW1 Mode revised 19.4.2.1 FMR00 Bit "... (including suspend periods) ..." added Figure 19.5 FMR0 Register NOTE6 added
Figure 19.7 FMR4 Register; NOTES 2, 3 and 4 revised and NOTE5 added Figure 19.8 Timing of Suspend Operation revised 19.4.3.1 Read Array Command "The MCU also enters read array mode after a reset." added 19.4.3.2 Read Status Register Command "The MCU remains in read status mode ... command is written." added 19.4.3.4 Program Command; "When suspend function disabled, ...", "When suspend function enabled, the FMR44 bit ... when auto-programming completes." added Figure 19.12 Program Command (When Suspend Function Disabled) title revised Figure 19.13 Program Command (When Suspend Function Enabled) added
376 380 384 386
387 388 389 394 395 397 399 401 402 405
406
407 408
19.4.3.5 Block Erase revised Figure 19.14 Block Erase Command (When Erase-Suspend Function Disabled) title revised Figure 19.15 Block Erase Command (When Erase-Suspend Function Enabled) revised Table 19.5 Status Register Bits revised 19.5 Standard Serial I/O Mode revised Table 19.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2) added
Table 19.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3) revised
409 410 413 414
C - 14
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 1.00
Date May 31, 2006
Page 415 416 420 421 422 423 424 425 426
Summary
Figure 19.17 Pin Connections for Standard Serial I/O Mode 3 title revised
Figure 19.18 Pin Processing in Standard Serial I/O Mode 2 added, Figure 19.19 Pin Processing in Standard Serial I/O Mode 3 title revised 19.7.1.7 Reset Flash Memory deleted Table 20.2 Recommended Operating Conditions revised Figure 20.1 Ports P0 to P4, P6 Timing Measurement Circuit; title revised
Table 20.4 Flash Memory (Program ROM) Electrical Characteristics revised
Table 20.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics revised Figure 20.2 Time delay until Suspend title revised Table 20.9 Voltage Monitor 0 Reset Electrical Characteristics Table 20.9 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics revised Table 20.10 Power-on Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 0 Reset) deleted Figure 20.3 Power-on Reset Circuit Electrical Characteristics revised Table 20.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics revised Table 20.11 Low-speed On-Chip Oscillator Circuit Electrical Characteristics revised Table 20.16 Electrical Characteristics (2) [Vcc = 5 V] revised Table 20.22 Electrical Characteristics (4) [Vcc = 3 V] revised Table 20.28 Electrical Characteristics (6) [Vcc = 2.2 V] revised 21.1.1 Stop Mode and Wait Mode revised and 21.1.4 fOCO40M deleted 21.2.7 Entering Wait Mode after Oscillation Stop Detection Interrupt is Detected deleted 21.3.2 Notes on Timer RB; "* ... Timer RB starts counting at the first ... 1 (during count)." deleted "* When the TSTOP bit in the TRBCR register ... immediately stops. * If the TOSST bit or the TOSSP bit ... also be set to 0 or 1." added 21.3.3.1 TRDSTR Register (i = 0 or 1) revised
21.3.3.6 Reset Synchronous PWM Mode; Change procedure (2) revised 21.3.3.7 Complementary PWM Mode; *Change bits CMD1 to CMD0 in the TRDFCR register in the ...; Change procedure: When setting to complementary ... (2) , Change procedure: When stopping complementary ... (1) and (2) revised *Do not write to ...; "However, set to the TRDGRD0, ... BFD1." added
427
434 438 442 445 448 450
451 452
456 462 463 466
21.3.3.8 PWM3 Mode deleted 21.6 Notes on Hardware LIN; "Sync Break" "Synch Break" revised 21.7 Notes on A/D Converter revised 21.8.1.7 Reset Flash Memory deleted
C - 15
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 1.00
Date May 31, 2006
Page 468 469
Summary 22. Notes on On-Chip Debugger; (2) revised Appendix 1. Package Dimensions "The latest package ... Renesas Technology website." added
2.00
Nov 01, 2006
all pages "PTLG0064JA-A (64F0G)" package added Y version added Factory programming product added 1 2, 3 1. Overview; "... or a 64-pin molded-plastic FLGA." added Table 1.1 Functions and Specifications for R8C/24 Group, Table 1.2 Functions and Specifications for R8C/25 Group; Package: "64-pin molded-plastic FLGA" added Figure 1.4 PLQP0052JA-A Package Pin Assignments (Top View); NOTE3 revised Figure 1.5 PTLG0064JA-A Package Pin Assignments added Table 4.1 revised Figure 6.5 NOTE6 revised Table 7.17 revised Table 7.19 revised Table 7.33, Table 7.35 revised Table 7.36 revised Figure 10.5 NOTE2 added Figure 10.8 NOTE6 revised Figure 10.9 revised 10.2.2 "Adjust the FRA1 register so that .... 40 MHz or less." added Figure 10.11 revised Figure 10.12 revised Figure 10.13 revised 10.7.1 revised, 10.7.2 added 12.6.3 "and Table 20.18 (VCC = 5V), ... TRAIO Input, INT1 Input." deleted Figure 13.2; Watchdog Timer Control Register: After Reset "When read, the content is undefined." added Table 14.4; TRAO pin function: Specification "or pulse output" added Figure 14.49 NOTE2 added Figure 14.65 Timer RD Output Control Register NOTE2 added Figure 14.71 revised Figure 14.100 NOTE2 added 14.3.12.7 "Do not use the TRDGRC0 register in complementary PWM mode." deleted Table 15.1 NOTE2 revised Table 15.4 NOTE1 revised
9 10 18 36 61 62 66 67 78 80 81 82 90 91 93 98 123 127 140 198 215 220 252 262 291 296
C - 16
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 2.00
Date Nov 01, 2006
Page 298 306 337 Figure 15.10 revised Figure 16.3 NOTE2 revised Figure 16.26 NOTE3 revised
Summary
344 to 349 Figure 16.32, Figure 16.33, Figure 16.34, Figure 16.35, Figure 16.36 revised 370 374 375 377 378 384 395 396 411 413 416 425 432 Figure 17.5 revised Figure 17.9 revised Figure 17.10 revised 17.4.4 added Table 17.2 Cause of Interrupt "8" "6" Table 18.2; Stop condition: Specification "when the ADCAP .... (software trigger)" added, Input pin: Specification "AN8" "AN0" Figure 19.1 revised Figure 19.2 revised Figure 19.13 NOTE3 added Figure 19.15 NOTE3 added Figure 19.16 revised Table 20.1 Absolute Maximum Ratings; NOTE1 added Table 20.10; "VCC = 4.5 V to 5.5 V -20C Topr 85C", "VCC = 4.5 V to 5.5 V -40C Topr 85C" added Oscillation stability time: Condition "VCC = 5.0 V, Topr = 25C" deleted Table 5.11; Oscillation stability time: Condition "VCC = 5.0 V, Topr = 25C" deleted Table 20.15; IIH, IIL, RPULLUP Condition: "Vcc = 5V" added Table 20.16; Condition: High-speed on-chip oscillator mode revised Table 20.17 added Figure 20.8 revised Table 20.22; IIH, IIL, RPULLUP Condition: "Vcc = 3V" added Table 20.23; Condition "Increase during A/D converter operation" added Figure 20.12 revised Table 20.29; Condition "Increase during A/D converter operation" added Figure 20.16 revised Package Dimensions; "PTLG0064JA-A (64F0G)" added "RENESAS TECHNICAL UPDATE" reflected: TN-16C-A164A/E, TN-16C-A165A/E, TN-16C-A166A/E, TN-16C-A167A/E Table 1.1, Table 1.2 Clock; "Real-time clock (timer RE)" added Table 1.3, Table 1.4 revised Figure 1.2, Figure 1.3; ROM number "XXX" added Figure 3.1, Figure 3.2; "Expanded area" deleted
438 439 440 441 443 444 445 448 449 475 3.00 Feb 29, 2008
-
2, 3 5, 7 6, 8 16, 17
C - 17
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 3.00
Date Feb 29, 2008
Page 18 27 27, 128, 401 28 29 30 36 61, 62 65 70 73 74 75 78 79 80 81 83 88 90 92 94 96 99 103 105 115 120 124 125 133 134 138 149 150 153 156 Figure 5.3 revised
Summary Table 4.1; "002Ch" added, "003Bh" "003Ch" "003Dh" deleted Figure 5.4, Figure 13.2, Figure 19.4; "OFS Register" revised 5.1.1, 5.1.2; "Wait for 1/fOCO-S x 20." "Wait for 10 s or more." Figure 5.5, Figure 5.6 revised 5.2, Figure 5.7 revised Figure 6.5 NOTE6 revised Table 7.17, Table 7.19 revised Table 7.29, Table 7.30 revised Table 7.48 revised 10. "(with oscillation stop detection function)" deleted Figure 10.1 revised Figure 10.2 NOTE4 revised Figure 10.5 NOTE2 revised Figure 10.6 "FRA7 Register" added Figure 10.8 NOTE6 revised Figure 10.9 added 10.2.2 revised 10.5.1.2, 10.5.1.4 revised Table 10.3 revised 10.5.2.5, Figure 10.13 revised Figure 10.14 revised 10.6.1 revised 10.7.1, 10.7.2 revised 12.1.3.1 revised Table 12.2 "Reference" revised 12.2.1 revised Table 12.6 revised, NOTE2 added 12.6.4 deleted Figure 12.20 NOTE2 revised Table 14.1 "* fC32" deleted Figure 14.1 "TSTART" "TCSTF" Figure 14.5 "... to 0 (During count)." "... to 1 (During count)." 14.1.6 revised, "* When the TRAPRE ..." "* When the TRA ..." added 14.2 "The reload register ..." deleted Figure 14.12 revised Table 14.15 revised Figure 14.17 "... to 0 (During count)." "... to 1 (During count)."
C - 18
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 3.00
Date Feb 29, 2008
Page 159
Summary Table 14.9 NOTE2 added "...0 (one-shot stops)." "...1 (one-shot stops)." "TRBP pin function" "TRBO pin function" Figure 14.20 "... When write, ..." "... If necessary, ..." Table 14.10 NOTE2 added
160 164
167 to 170 14.2.5 revised 14.2.5.1, 14.2.5.2, 14.2.5.3, 14.2.5.4 added 197, 214 Table 14.25, Table 14.27; "at the same time as the TRDi register ... 0000h" deleted 198, 215 Figure 14.47, Figure 14.63; "TRDSTR register" revised 201 206 209 212 214 220 Figure 14.50 "TRDOER1 register" revised Figure 14.55 revised Figure 14.59 "of counter clear" deleted Figure 14.61 revised Table 14.27 revised Figure 14.68 revised
227, 251 Table 14.29, Table 14.33; "at the same time as the TRD0 register ... 0000h" deleted 228 232 238 239 243 252 257 261 264 277 286 291 293 300 303 304 308 309 310 311 312 313 Figure 14.76 revised Figure 14.80 revised Figure 14.86 revised Figure 14.87 revised Figure 14.91 revised Figure 14.98 "TRDSTR register" revised Figure 14.103 revised Figure 14.107 revised 14.3.12.1, Table 14.36; "after the count is cleared" deleted Figure 14.121 "00" "00b" Figure 14.130 revised Figure 15.4 "UARTi Transmit/Receive Mode Register" NOTE2 deleted Figure 15.6 "(b7-b4)" "(b7-b6)" Table 15.5 NOTE2 added Table 15.7 revised 15.3 revised Figure 16.2 NOTE4 deleted Figure 16.3 revised, NOTE4 deleted Figure 16.4 NOTE2 deleted Figure 16.5 NOTE1 deleted Figure 16.6 NOTE2, NOTE7 revised Figure 16.7 NOTE5 revised C - 19
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 3.00
Date Feb 29, 2008
Page 314 328 334 338 339 340 341 342 367 368 373 374 375 377 379 380
Summary Figure 16.8; SSTDR register: NOTE1 deleted, SSRDR register: NOTE2 deleted Figure 16.18 revised 16.2.8.1 deleted Figure 16.24 NOTE6 revised Figure 16.25 NOTE5 deleted Figure 16.26 NOTE7 deleted Figure 16.27 NOTE3 revised Figure 16.28 NOTE7 revised 16.3.8.1 revised, 16.3.8.2 added Figure 17.1 revised Figure 17.5 "... in LINST register 0" "... in LINST register 1" Figure 17.6 revised Figure 17.7 revised Figure 17.9 revised Figure 17.11 "SCDCT" "BCDCT" Figure 17.12 revised
343, 344 Figure 16.29, Figure 16.30; NOTE1 deleted
385, 388, Figure 18.2, Figure 18.4, Figure 18.6; NOTE4 revised 391 394 396 397 402 403 404 405 406 408 410 411 413 414 416 418 420 429 435 454 Figure 18.10 revised 18.7 revised Table 19.2 revised Table 19.3 revised 19.4.1, 19.4.2; "(SR-ES)" "(SR-SUS)" 19.4.2.4 "located outside ... memory." "transferred to the RAM." 19.4.2.15 revised Figure 19.5 NOTE3, NOTE5 revised Figure 19.7 NOTE5 revised Figure 19.9 revised Figure 19.11 revised 19.4.3.4 revised Figure 19.13 revised Figure 19.15 revised Table 19.6 "FRM00 Register" "FRM0 Register" Table 19.7 revised Table 20.2 NOTE2 revised Table 20.10 revised, NOTE4 added 21.1.1, 21.1.2 revised
C - 20
REVISION HISTORY
R8C/24 Group, R8C/25 Group Hardware Manual
Description
Rev. 3.00
Date Feb 29, 2008
Page 455 456 458 21.2.4 deleted Figure 21.1 NOTE2 revised
Summary
21.3.1 revised, "* When the TRAPRE ..." "* When the TRA ..." added
459 to 462 21.3.2 revised 21.3.2.1, 21.3.2.2, 21.3.2.3, 21.3.2.4 added 463 470 472 473 475 482 483 21.3.1.1, Table 21.1; "after the count is cleared" deleted Figure 21.8 revised 21.4 revised 2.5.1.1 deleted, 2.5.2.1 revised, 2.5.2.2 added 21.7 revised Appendix Figure 2.1, Appendix Figure 2.2 revised Appendix Figure 3.1 revised
C - 21
R8C/24 Group, R8C/25 Group Hardware Manual Publication Data: Rev.0.10 Rev.3.00 Jul 27, 2005 Feb 29, 2008
Published by:
Sales Strategic Planning Div. Renesas Technology Corp.
(c) 2008. Renesas Technology Corp., All rights reserved. Printed in Japan
R8C/24 Group, R8C/25 Group Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

▲Up To Search▲

Price & Availability of R5F21258SDFP

	To Download R5F21258SDFP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .